PM0056, Rev 6, page 91, Table 30. Branch and control instructionsCBNZ Compare and Branch if Non ZeroCBZ Compare and Branch if Non Zeroreally ?but later :3.8.6 CBZ and CBNZCompare and branch on zero, compare and branch on non-zero.
Hello,I think that I found an issue in the HAL code generated by CubeMx 6.6.1 with STM32L4.I2C HAL in file stm32l4xx_hal_i2c.c line 6855 there is an infinite loop : while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { /* Check for...
Hi, on my board i`m running bootloader in internal flash of stm32h750 together with 2 QSPI NOR chips that store main program.Bootloader starts and jumps to main program in QSPI, howeverit get`s tricky when this function is called:SystemClock_Config()...
I am using the UART of STM32H747,with DMA transfering data. There is a Note in the reference manual about DMA_SxCR register:And in the Errata sheet of STM32H743, it says:What does a concurrent transfer mean? Will the DMA channel transfering UART data...
I have a 32f769i-disco board that has limited pins exposed on an arduino connector. I need what is termed a "capture compare timer" and I'm not sure I understand it. the capture compare time was used on the arduino version of this code.1) I've setu...
I realise that with ADC timer triggered DMA of 32 samples, you can set the timer precisely, but not the ADC per sample clock, so the samples get bunched up or stretched in the frame. The number of clocks per sample is limited, adjusting the APB2 clo...
The data sheet for this family of parts mentions a Quad-SPI, butaccording to the datasheet the QFPN32 package does not appear to have QUADSPI_BK1_IO0 exposed to a pin (see picture). The Quad-SPI configuration in 1x/2x/4x IO mode all appear to requir...
Hi,Context:I've hit a roadblock in using the stm32h743VG.According the reference manual, this is the FLASH memory mapping: I'd like to focus your attention on the address gap between Bank1 & Bank2.To alleviate this, I've first done the following:MEMO...
