Pending interrupt in NVIC ''reappears'' after being cleared
Posted on August 22, 2012 at 14:09The following code (TIM3 has clock enabled in RCC but otherwise is in its reset state):#define TEST_TG #ifdef TEST_TG TIM3->DIER |= TIM_DIER_TIE; // enable interrupt from trigger TRGI #else TIM3->DIER |= TIM_D...