RCC_CFGR_HRPE Bit? (SysClk Devider)
Posted on March 28, 2013 at 10:12Hi, in the file System_ST32F4xx.c of the ST4Discovery examples, I always find the following 2 lines for the clock configuration (SysClk 168MHz): /* HCLK = SYSCLK / 1*/ RCC->CFGR |= RCC_CFGR_HPRE_DIV1; ...