Posted on October 23, 2013 at 21:20Using the 3 channels of the SDADC in Single Ended Zero Reference Mode, Gain 1, with a SDREF at 2.5V. Spec lists gain error of -2.4% to -3.1%, but our devices appear to have a positive gain error of approx +2.8%. ...
Posted on November 22, 2013 at 00:44Hi there, I've got a problem here using NVIC_SetVectorTable(). I have attached my test programm, which is held very simple and does: - Init Leds&UserButton - make sure the ''new'' Vectortable is 0x200-aligned - Co...
Posted on November 21, 2013 at 16:23Hello, I have a problem with the RCC_ADCCLKConfig, I want to change the ADC frequency and I followed the example from st. /* Configure the ADC clock */ RCC_ADCCLKConfig(RCC_ADC12PLLCLK_Div64); /* Enable...
Posted on November 22, 2013 at 15:45error fatal can not connect to j link via usb
Posted on November 22, 2013 at 14:34 Hello, I wrote this code to test mic and the codec but I don't here any thing :\ If some one can helpe me. /* config Codec*/ I2S_InitTypeDef I2S_InitStructure; GPIO_InitTypeDef GPIO_InitStruct...
Posted on November 22, 2013 at 11:57 The stm32 chip has a error for I2S in slave mode (stm32f40x Errata sheet 2.4.1). 2.4.1 In I2S slave mode, WS level must be set by the external master when enabling the I2S Description In slave mode, th...
Posted on November 21, 2013 at 22:08Hello Everyone,I'm new to the IAR Embedded Workbench IDE (IAR embedded workbench for arm V 6.70.1.5794, common components version 6.6.5.2892). I have the STM32L152C discovery board and a ''Hello World'' sample p...
Posted on November 21, 2013 at 21:05We are using the STM32F101RD component. We've configured TIM5, channels 2, 3 and 4. Channels 2 and 4 work as expected. Channel 3 is always high (we have 10k pull ups on the line) and is never driven low by the ...
Posted on November 21, 2013 at 12:42The original post was too long to process during our migration. Please click on the attachment to read the original post.
Posted on November 21, 2013 at 15:25Hi, I would like to ask if there is a way to clear the FRLVL and RXNE bits in SPIx->SR in order to ignore everything that has been received before. I have some routines that only send data and other that will als...
