ADC with DMA Half Conversion complete and Conversion complete callback not aligned.
Hello,i set stm32f103c8 adc1 at 12mhz . Main clock is 8Mhz * 9 = 72Mhz.i use ADC_SAMPLETIME_7CYCLES_5 so 12.5 + 7.5 = 20cycle = 600ksps.i set dma circular continuous mode with 1000 element buffer.i can receive half and conversion complete interrupts ...