NVIC_SCBDeInit is in contraddiction with Cortex manual (??)
At the end of NVIC_SCBDeInit I see these instructions:[...]SCB->CFSR = 0xFFFFFFFF;SCB->HFSR = 0xFFFFFFFF;SCB->DFSR = 0xFFFFFFFF;The first one is a status register. Why writing it?For the second one the manual states:"This register is read, write to c...