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Hello,in AN4539, the HRTIM cookbook, on page 56 C.3, the application note AN5094 "Migrating between STM32F334/303 lines and STM32G474xx/G431xxis" is mentioned. Unfortunately, i cannot find this document. Any suggestions?Kind regards,Greg
RM0440 states in 46.8.3 that SW-DP ID code is 0x1BA01477. However, it's actually 0x2BA01477.
RM0440 Rev 3 (last version) recomend to set 4WS for 170MHz CPU clockRM0440 Rev 2 recomend to set 8WS for 170MHz CPU clockST driver library (STM32G4xx_HAL_Driver) function LL_PLL_ConfigSystemClock_HSE() set 8WS for 170Mhz clock. Which Flash WS setting...
STM32G4 CPU speed. I am migrating a project from the STM32F405RG to the STM32G473RE. System clock frequency for both is 168MHz. I have found the code runs at about half speed on the STM32G473 and I would like to know why and how to fix it.The STM32G4...
Hello,I'm working on a project involving the STM32L471 device clocked at 80Mhz (Externalcrystal oscillator with internal PLL).We are using ADC1, also clocked at 80Mhz (CKMODE = 0x01)We are noticing an issue concerning the calibration (and the consequ...
Hi, I am trying to get working IWDG using HAL_IWDG library and I am not able to refresh the watchdog before IWDG_Reset. As is said in page 6: (https://www.st.com/content/ccc/resource/training/technical/product_training/group0/01/24/22/29/38/70/40/57/...
This question may applied to the whole STM family and maybe pure hardware related, but I expect someone can give some clues.May I safely assume the gpio pins are high impedance when powering on?If I set pin to output, and output a high. Then, the p...
Hi, any reply is greatly appreciated. I intend to interface ov7670 with my nucleo board for a qvga with yuv422. To get 30 frames per second ,the pclk must be set to 24Mhz(according to the data sheet). What this means is that each byte is received fro...
Hi, I looking for BOOT0 pin from the NUCLEO-G071RB. I want to change the boot configuration then turn the BOOT0 pin to HIGH. So, I could reach the system memory boot. But, the errata sheet says that Under Level 1 read protection, booting from Main Fl...
It says specifically in datasheet that it does, but when I create new STM32CubeIDE project and select STM32F730V8, FMC only offers PSRAM/NOR Flash/LCD interface. I tried for testing purposes selecting some other MCU that also supposedly supports SDRA...
