I remember seeing a flowchart showing the order in which interfaces are checked for activity during programming when the BOOT pin is pulled, but I have been through the datasheet, programming manual and Google and can't find it now. Can anybody poin...
In 15.5.12, the register definition for mdma_ctbr , i am having trouble understanding the dbus and sbus bit descriptions. Shouldn't the choices be between tcm/axi and ahb/system and not system/axi and ahb/tcm as the latter is mixing the domains toget...
Hi,I have some problems with UART4 on STM32H750. Uart4 is asynchronous RS485 mode mapped on PC11,PC10 and PA15 (DE).I tried to SWAP RX/TX without succeed. Finally, I swapped it by wire.DMA not working properly. DMA Counter works. Memory address neve...
Hello,in my project I connected 6 channels to ADC3; then i set up:A single mode regular sequence to read 5 of them using DMA; start of sequence is given by software inside a periodic task An injected sequence for the 6th channel to trigger a conversi...
I am using stm32F103C8T6 controller, How to configure ATWINC1500 for WiFi establish?Please help me for how to develop connection between stm32F103C8T6 to ATWINC1500.
I am using STM32F105 (25Mhz crystal freq)with atmega16. cycle of data sending:1.STM32 to ATMEGA16.2. ATMEGA16 to STM32.first cycle is working fine but in second cycle atmega send data perfectly but stm32 not receive receive continue data.
Hello, i am going through the the technical reference manual of STM32L4R5 and i am bit confused about the Flash Protection feature, specifically write protection feature.my product requirement is to avoid the modification of my executable ( bootloade...
stm32h743iiWhen we set the OSPEEDRy[1:0] = 11 we have glitch spike (undershoot) on clock and data. it was improved when we set OSPEEDRy[1:0] = 01.In datasheet SPI interface characteristics page 307 saidOutput speed is set to OSPEEDRy[1:0] = 11.
