Static latch-up test as per JESD78A, which over-voltage profile is applied during the test?
The STM32F407xx datasheet (DocID022152 Rev 8) specifies on page 113 that a supply overvoltage is applied to each power supply pin, in conformance to the EIA/JESD 78A. What is the applied voltage profile? The standard specifies 1.5 x Vmax for a T up t...