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Hello!I want to use CPU1 (CM7) doing the following:1) Hold CPU2 (CM4)2) Flash new firmware for CPU23) Reset and release CPU2.During this process CPU1 must be able to keep communicating to a Host via Ethernet / lwip.______________________________I can...
Hello,Issue :- STM32L4R5 controller will restarting, because of the IWDG in stop1 mode of MCU.Approach followed : As per reference manual, by clearing the IWDG_STOP bit of FLASH_OPTR register, we can freeze the IWDG counter in stop 1 mode of the MCU....
I am facing a realy strange problem while trying to put my stm32f103c8t6 into a standby mode. The consumption in standby mode is .8mA (what is 40 times higher then its supposed to be) on first board (Board A) and .02mA (what is 10 times higher) on se...
I already know timer3 has not like timer 1 and 8 dead time generation featur. but maybe there is a way to add it!
The LoRaMac reference implementation get a DEVEUI from the STM32L072 Unique device ID registers (96 bits) registers.Coudl please confirm if the Unique Device ID is available for the CMWX1ZZABZ-091?BRGilberto
Could you please tell me the reliability data of STM32F103RET7 as MTBF or FIT?
I'm working on a custom boot loader for a STM32F429, where I want to reserve the second of the first four 16K flash sectors for user data. Because the vector table has to start at 0x08000000, the memory layout would look like this:0x08000000 - isr ve...
I have a very peculiar problem with my STM32F745 MCU. I have generated code with CubeMX which is very basic and doesn't initialize any peripherals at all. Main simply initializes the HAL, clock & then goes into an infinite loop that increments a coun...
What is the silicon revision of the chip on currently shipping Nucleo-H7A3ZI-Q?
Posted on February 13, 2016 at 11:22Hello!I have the follow problem:I use STM32F745. I've chosen the QuadSPI interface for flash, to be exact, QSPI BANK2. I make initialization through CUBEMX, using HAL library. I see CLK signal only, there are no o...
