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I've been trying to use the TIM2_CH1 function for PA15 but without success on a Nucleo-L073RZ. This function works OK on pins PA0 and PA5. Also PA15 works if set in GPIO output mode.Errata document does not state anything about this pin.Could you con...
I have an STM32H747i-Disco board and looking at the ADC example (which I have compiled and ran successfully)The example uses channel 18 and GPIO PA0_4 as both master and slave ADC inputs.I would like to use PA0_C and PA1_C as the two ADC inputs but I...
Hi,I'm attaching a picture of my clock configuration and Logic Analyzer (Saleae Logic Pro 8) so it is easier to see what I'm doing.I have set the SDMMC clock divide factor to 1 in the configuration tab, which should produce a divide factor of 2 in th...
Hi,Using STM32G474RE board (Nucleo-64). I have tried a lot of different things to configure VREFBUF and none of them have any effect.I'm outputting two voltages on DAC1 at 75% scale and 25% scale and they are always relative to approx 3.25V (which is...
Hi I am tryingthe spi dma example for stmH7 nucleo board, it is always takes me to the SPI_DMAAbortOnError function, and it looks like it is because it gives HAL_SPI_ERROR_UDR, any idea what could have caused it? For my master I am using 1Mbps clock ...
Hello, I am using an STM32L432KCU and I trying to use the TIM2_CH1 output as a re-triggerable output with TIM2 ETR input connected to COMP1_Output.The configuration done by STM32CubeIDE (version 1.3.0, build 5720_20200220_1053 (UTC)) is the following...
下�?�是我的代�?void TimerInit(){ TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; NVIC_InitTypeDef NVIC_InitStructure; RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE); TIM_DeInit(TIM3); TIM_TimeBaseStructInit(&TIM_TimeBaseStructure); TIM_TimeBaseStruct...
Hi all,I want to use timer 2 to trigger ADC function (ADC3) on STM32H743ZI2 platform. After DMA & timer starting, I stuck in HAL_ADC_IRQHandler(). /* Multimode not set or feature not available or ADC independent */ if ((hadc->Instance...
i would like know the cause of reset during the power on stage for may application.i would like to differentiate if its power on reset/NVIC reset/WDG reset or any other cause?