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Posted on February 12, 2018 at 19:29I'm about to use a STM32F7 MCU with some x16 SDRAM. Since I don't use byte or unaligned accesses, I disabled the NBL pins, which should otherwise be connected to DQMH/L at the SDRAM.But if I don't use those signal...
I am using the STM32F429 and interfacing some SDRAM which i have done before with no problem but in 16 bit mode. So the NBL0 and NBL1 where connected to the SDRAM and the system works very well. Due to needing a few extra pins for general IO i am dro...
I have created an IAP to load our application and jump to the application which appears to work as expected when the IAP is run from the IDE Debugger. Now I need a way to jump from the application to the IAP to instigate the loading of a new applicat...
HiIn your Reference Manual for the STM32F469 at 31.3.11 it says:A DMA access is requested when the TXE or RXNE enable bit in the SPIx_CR2 register is set.But the SPIx_CR2 Register does not have a TXE/RXNE bit, it has a TXEIE/RXNEIE bit which just en-...
I need to calibrate the internal timer to do ADC sampling using GPS receiver.The accuracy of measurement is most important (zero or minimum jitter), PPS output of GPS receiver is input.Thanks in advance
I have created a simple project, where I need to get the interrupt at exactly 1us.Please find attached an image of the clock configurations that were created in STM32Cub3MX.I am using TIM3 which is associated with APB1, so the MAX frequency for this ...
Hi,I am using STM32L4S5ZI which has only a timer with maximum capacity of 32-bit. The DWT(Data Watchpoint Trigger) is somehow not available because when I check for DWT->CNT it always shows 0. So I needed a 64-bit timer for my application which keeps...
Hello everyone;I'm working LUPART with STM32H747. I have a problem like this;- LPUART 1000000 baudRate has been installed. LSE clock is not used.There is no problem when the LPUART's RX-TX line is physically connected to the module. But when I physic...
HiI just wonder at the example:STM32Cube_FW_F4_V1.26.0/Projects/STM32469I-Discovery/Examples/FMC/FMC_SDRAM/Src/main.cand there is a define:#define WRITE_READ_ADDR ((uint32_t)0x0800)Whats the purpose of that (offset?)? Doesn't the FMC SDRAM start ...
