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Resolved! STM32H753: How is an ECC in the L1 caches reported

Hi,I'm currently working on a STM32H753. I'm trying to figure out how an ECC error upon a cache look up is reported. The cortex M7 reference manual doesn't provide much info in that regards with the following text:Each cache can also be configured wi...

DBine.1 by Associate
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Resolved! BSP testing

Hi AlWondering how do you test the infrastructure before delivering it to the application teams?I’m basically referring to the HAL layer , CMSIS and all BSP layer with peripherals.Is there a known methodology for validation tests for these capabiliti...

deckhard by Associate III
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STM32G070RB, Maximum Alarm length

What is the maximum alarm length in the G070. I only see about 30days.I need 6 months.I guess I could implement one using the TAMP_BKPxR registers and compare the RTC DR , TR with the alarm values I have store in the TAMP regs. ( stripping out the W...

MEder by Associate III
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STM32H743 Nucleo board SEGGER JLink issue

Hi There, I bought two STM32H743 Nucleo boards recently and did some tests on them. As usual, I first converted ST-Link v2 to JLink interface using the tool SEGGER provided. I have done this with F1, F4, and F7 series boards in order to use JLink RTT...

XZ by Associate II
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TIMER with DMA call back function

Hi,void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim){ if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_1) {  captureDone = 1; }}HAL_TIM_IC_Start_DMA(&htim2, TIM_CHANNEL_1, (uint32_t*) captures, 2);void HAL_TIM_IC_MspInit(TIM_HandleTypeDef* htim_ic){...

NPULI.1 by Associate II
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