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Hello, I am working on adding an IWDG to firmware on a STM32F070CBT6TR. The Watchdog resets perfectly fine. I cause the watchdog to reset the MCU by not resetting the timer. I then try to read the RCC_FLAG_IWDGRST and it is always 0. This is what my ...
Hello Support, I am not able to find the QSPI config in the STMCube 1.18.1version. I have attached the snapshot. According to the EvalBord it supports QSPI. CAN you guide me here for the setup. Best Reagrds, Manikanta
Hi,We are working with the STM32G491 board and intend to drive the NRST pin using an external device. Could you please confirm the minimum low-level pulse duration on the NRST pin for it to be recognized as a valid reset by the MCU?
The chip is H743. After performing a erase operation on a page and resetting it, when I read the page again, the debug page shows that the erased page is 0xAA. As long as I read it, I will enter hardfault. Have you ever encountered a big shot,
I would like to ask about the current load. I expect to use three sets of SDADC, SPI, and USART, all of which will use DMA for transfer and operate at a frequency of 11000HZ. The clock will use an external 12M crystal oscillator. I estimate from offi...
Hi everyone,I’ve designed a schematic based on the STM32G0B1CE microcontroller. Since there’s no official development board available for this specific MCU, I used the schematic of the STM32G0B1RE Nucleo board as a reference, along with the STM32G0B1...
I've been trying to find examples of the STM32N6 using the internal SMPS however, other than trying to reverse engineer the Nucleo or Discovery boards, there doesn't seem to be much literature available showing this.Ideally (for cost and board layout...
Hello, I just designed an electronic card using the STM32G474QET6TR. Just a day before receiving the card I realised I had made a mistake on the routing. I want to use SPI2 to driver 2 MAX4896ETP+ that are daisy chained.As per the MAX datasheet, to d...
According to erratum 2.22.10 of STM32H562xx/563xx/573xx in RMII 10MHz mode packets should be accepted when both dribble and CRC error is flagged. According to Reference Manual RM0481 Rev4 Table 692 dribble bit is valid in MII mode only. Pls. clarify ...
Hello, I'm trying to use the repeat counter of the 2D GPDMA peripheral. However, when I configure this with CubeMX and run it, I can see that the BRC register is always at zero, while the BNDT register is set to the correct value. I've stepped throug...
