Forum Posts
reading processor VRefInt voltage
Posted on October 22, 2012 at 11:39I want to measure ADCx_IN17 (internally connected to processor VRefInt). What sample time should I use ?
UART4 Interrupt
Posted on October 22, 2012 at 03:45Hello, I am working on STM32F4Discovery Board. I am trying to make the UART4 connection with interrupt. I have declared all the needed settings but not able to find the problem. The problem is that it doesn't go t...
Programming,
Posted on October 21, 2012 at 19:43I have a problem with programming a Stm32f0Discovery board,When i have a code built and the board connected with STM32 ST-LINK Utility, and i click program it says: No Stlink detected.What am i doing wrong,
[Question] STM32F0 cotex-M0 i2c master init (attached file- code/clock images)
Posted on October 22, 2012 at 14:13I am trying to make i2c driver with stm32f0 cotext M-0. I am a very newer. I am reading specification, RM0091 and following the instruction. I set STM32f0 i2c as a master and I followed the RM0091 (24.4.9 I2C maste...
High Speed IO?? Is it really true?
Posted on October 22, 2012 at 13:20Hi all,I bougth a STM32F2 evulation board and iam trying to use high speed IO's but i didnt succes. here is the code;RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOF, ENABLE); /* Configure PG6 and PG8 in output pushpul...
STM32 RC5 STOP MODE ???
Posted on August 06, 2011 at 02:56I want to use low power mode (STOP). i put two configurations here... In the first configuration i am putting 2 STOP mode but first runs... When i wait the same external interrupt despite i enable this, i cant run b...
Circular DMA does not circle for ADC (STM32L1xx)
Posted on October 19, 2012 at 17:49I'm trying to use the ADC on an STM32L1xx to read a single channel with a sample rate based on TIM2. I plan to use a double-buffering scheme, so I want to set it up to DMA into a buffer with half-complete and full...
1 external RAM shared between 2 separate FSMCs
Posted on October 16, 2012 at 17:14Hi all, I'd like to make 2 STM32F407 share 1 external RAM as a common memory. Chip #1 would store some data in RAM for chip #2, then stop all accesses and signal to #2 that there is some data for him. Chip #2 would...
Simultaneous DMAs: Poor docs or restrictive hardware?
Posted on October 19, 2012 at 18:51The STM32L1xx reference manual has this text in the DMA section: The 7 requests from the peripherals (TIMx[2,3,4,6,7], ADC1, SPI[1,2], I2Cx[1,2], USARTx[1,2,3]) and DAC Channelx[1,2] are simply logically ORed...