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ADC Dual - Scan - Continuous mode at the same time ??

Posted on September 03, 2015 at 09:18Hi. Does anyone know, if it's possible to use the mentioned combination? I have 8 Channels - 4 on ADC1 and 4 on ADC2. If I have Continuous mose disabled, it works nicely. I make two parallel AD sequences on both ...

matic by Associate III
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STM32L4 OTG_FS_VBUS issues again

Posted on September 01, 2015 at 22:23I am planning to use STM32L4 on a device powered by two alkaline batteries, and I'd like to use USB OTG. After reading the docs, i have came across a few problems:The first problem is the limitation regarding the...

dimitri by Associate II
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window watchdog in stm32f103

Posted on September 02, 2015 at 22:29hi every one I'm trying to initial stm32f103rbt6's window watchdog with keil cmsis examples, every thing is OK but in reverse direction,i mean it seems external interrupt & wwdg interrupt handlers are act instead...

mhdizgah by Associate II
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Barracuda App Server for 32F746GDISCOVERY

Posted on September 02, 2015 at 21:56Barracuda Application Server Demo for the Discovery Board(32F746GDISCOVERY)The Barracuda Application Server Demo includes a web based code editor, where you can develop your server side web application directly i...

wilfred by Associate
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STM32 SPI Spoiled Bits

Posted on October 06, 2014 at 13:11 Hello, I have a problem trying to communicate with SPI using the STM32 Nucleo. I am using the STM_HAL_Drivers to read data from an Invensense MPU9 When I read values, I sometimes get spoilage of the la...

0901123w by Associate II
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STM32F4Discovery SPI1 last bit problem

Posted on September 01, 2015 at 10:35Hello,I have a problem  with SPI1 using the STM32F4Discovery. The STM HAL(STM32Cube_FW_F4_V1.5.0 and V1.7.0  ) driver is used. When I use HAL_SPI_Transmit (master mode, bidirectional) last bit in returned byte is...

alevstiv by Associate II
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How to enable L1 cache on the stm32f746

Posted on September 02, 2015 at 18:32Hello. I want to enable L1 cache on the stm32f746 controller. In examples from STM32CubeF7 i found that memory protection unit enabled at first and then L1 cache. Is it necessary to enable MPU before L1 cache?

STM32CubeMX templates for Nucleo Boards

Posted on August 20, 2015 at 22:43Where can I find a template for the Nucleo boards; specifically the STM32F070RB-Nucleo and STM32F411RE-Nucleo offerings?   I am looking for the *.ioc file.

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Posted on September 02, 2015 at 14:35a