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New possibilities for the ultra-low power segment!

STM32U0 is the first Cortex-M0+ with a static consumption of only 160 nA in standby mode with RTC (Real-Time Clock) and 16 nA in shutdown. It also achieves 118 points in CoreMark and targets SESIP level 3 and PSA level 1 focusing on firmware code pro...

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Unstable working of I2S on STM32

Posted on August 08, 2013 at 21:17I faced a critical problem of i2s of STM32.I'm developing a simple system for i2s level meter.MCU - STM32F103RCT6 with external X-tal(12MHz), 72MHz of running clock Inpit Audio - 48KHz, 16bits, stereo i2s digital au...

cubefilm by Associate
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Vector table relocation

Posted on January 05, 2015 at 17:44I have relocated the Vector Interrupt Table as follows         *((volatile uint32_t *)0xE000ED08) = 0xFFFFFF00 & 0x08004400;                 // jump to bootloader         pVector = GetBootStartEntry();         asm ...

ivesely by Associate II
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Code generation tool for Std. Peripheral library?

Posted on December 20, 2014 at 16:41Hi everyone,I was wondering if there is a tool like STM32CubeMX to generate initialization code with the standard peripheral library.The Cube is too new and still needs to mature but i do like the STM32CubeMX tool...

STM32L0 GPIOA_MODER A4 default value

Posted on January 06, 2015 at 11:20Hello, the STM32L0 series sets nearly all GPIO to analog mode as default. This does make sense opposed to the ''default to input'' on other family that may result in high current draw with floating inputs. Only Por...

AHBxENR and AHBxLPENR

Posted on January 06, 2015 at 11:06Hello, how is the relation between AHBxENR and AHBxLPENR? If some clock is disabled in run-mode, it is automatic also disabled in sleep mode despite the related LPENR bit _not_ reset?. Or is it needed explicit to r...

SPI input value being interpreted incorrectly

Posted on January 04, 2015 at 04:11My project involves using a STM32L152 part as a SPI master that receives data from a slave (digital accelerometer). When I look at the SPI signals through a scope, I notice that the incoming SPI data is being inter...

bnp979 by Associate III
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