Posted on July 14, 2016 at 04:49Hi: Are there any documents mentioned about chip selection for upgrading from STM32F4 to STM32F7? I find a document AN4660 talking about migration, thus I know STM32F756 is the candidate. However is there any table ...
Posted on July 14, 2016 at 23:40I am using Keil. How should one determine what is the best size for the heap and stack? Are there any common guidelines? Thanks.
Posted on July 14, 2016 at 22:41 I'm attempting a fairly standard initialization of the SPI peripheral on an STM32F302, and for some reason whenever I call GPIO_PinAFConfig(GPIOA, GPIO_Pin_15, GPIO_AF_6), the program jumps to the WWDG_IRQHandler...
Posted on July 13, 2016 at 23:21So, the Cortex-M0 doesn't support tracing (so it doesn't support semihosting). The board has a TX & RX pin and a corresponding pair of solder bridges, but the manual says ''reserved''. So is it best to connect an exte...
Posted on July 14, 2016 at 17:27 I'm using an STM32L151 board and I want to know how to map a memory address to its function. For example: LDR.W R0, =0x20002A20 MOVS R2, #4 MOVS R1, #4 STR R1, [R0,#0x14] LDR.W R1, =0x20002224 STR.W R2, ...
Posted on July 13, 2016 at 14:31Hello, the HAL function HAL_CAN_Transmit_IT() enables the Transmit mailbox empty Interrupt before the requesting transmission. At least if I run the CAN bus wit 1Mbit the mailbox empty interrupt is triggered before th...
Posted on July 14, 2016 at 16:58 The cryptographic library for STM32 microcontrollers is certified according to http://csrc.nist.gov/groups/STM/cavp/index.html?_sm_au_=i5Mr1Z4bQW1kRZkV&icmp=tt3887_gl_pron_jul2016.An extension to the STM32Cube softw...
Posted on April 16, 2015 at 16:42I think i found an bug in the CAN driver. Explain me this:a) Receiving 1. In the example application HAL_CAN_Receive_IT is called from HAL_CAN_RxCpltCallback 2. Looking in the implementation of the driver we see that...
Posted on July 14, 2016 at 13:02Hi, I am working on STM32L073 board with a SPANSION NAND flash memory. I would like to implement a wear leveling system to it but seem like there is no example code inside the STM32CubeL0. Is there any wear leveling e...
Posted on July 14, 2016 at 14:51I have a Spartan-6 FPGA connected to an STM32F746IG using the FMC. The FMC is configured for SRAM in region 1.1 (0x60000000). I have disabled caching of the FMC region in the MPU. I see FMC read & write cycles with th...
