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Posted on November 09, 2016 at 14:58Hi all, I'm evaluating STM32F765 uc for my application and I need to clarify how the GP Timers are clocked.In other words, at page 38 of product datasheet, for TIM3 is wrote: Max Interface clock = 54MHz,...
Posted on October 17, 2016 at 09:15 Hai, I am using Stm32f030c8t6 and Quectel M35 modem moreover i am beginner in this one, I want to send text SMS to my number. I use Coocox Co Ide for code developing and here is my code, #includ...
Posted on November 10, 2016 at 09:58Hello all,I have a problem that driving me crazy. I'm using STM32F446 with case LQFP64. I'm not able to use PD2 as output digital even if with others PIN I can do it (PC0, PC1, PC2, ...). This is my code to set PD...
Posted on September 23, 2016 at 15:16To whom it may concern, RM0410 (DocID028270 Rev 2) for the STM32F76x tells on page 1484 in Table 258 about ''26 filter banks shared between CAN1 and CAN2'', while there are 28 registers and 28 banks in other devi...
Posted on November 04, 2016 at 11:23Hi,why the CAN2 start bank is limited from 1 to 27 in chapter 40.9.4 CAN filter registers - CAN filter master register (CAN_FMR) of the reference manual RM0410? I tested it with 0, so that the very first bank is a...
Posted on November 10, 2016 at 10:45 Hello anyone I working on OV9655 camera module that is connected to stm32f4discover evaluation board. I am able to capture a picture from the OV9655 module where the video output format is based on RGB565 a...
Posted on November 10, 2016 at 09:34I've implemented SDRAM access in stm32f103c8t6 using DMA.I notice that performance of the DMA when doing memory to peripheral transfer is quite a lot slower than I expected. The highest reliable clock I can run is...
Posted on November 08, 2016 at 07:33Hi!I have STM32F4discovery and PHY device LAAN8720. I want to configure the register with address = 0b00000 of the LAN8720. When I set PHY address = 0b00000 and after write operation of data 0x2100 I did read oper...
Posted on September 26, 2016 at 03:02The original post was too long to process during our migration. Please click on the attachment to read the original post.
Posted on November 10, 2016 at 05:14I'm attempting to write an interrupt based driver for I2C using just the CMIS header and my wits. My understanding is that there is a data register and a shift register. For transmission SR1.TXE means the data reg...
