STM32U0 is the first Cortex-M0+ with a static consumption of only 160 nA in standby mode with RTC (Real-Time Clock) and 16 nA in shutdown. It also achieves 118 points in CoreMark and targets SESIP level 3 and PSA level 1 focusing on firmware code pro...
Posted on January 17, 2018 at 11:30The STM32F4 has 4 Kbytes of backup SRAM.They seems not to be accesable at a certain adressThe HAL lib has also a driver for it. But the functions are not enabled default. The library stm32f4xx_hal_sram is needed fo...
Posted on March 05, 2018 at 05:29In Section 3.5.1 of the STM32F031 datasheet states:�The VDDA voltage level must be always greater or equal to the VDD voltage level and must be established first.�The statement �VDD voltage level and must be establis...
Posted on March 05, 2018 at 05:28Does ST have support for programmable logic in their micro-controller portfolio (like http://www.cypress.com/products/psoc-5 or http://www.microchip.com/design-centers/8-bit/peripherals/core-independent/configurable-...
Posted on December 16, 2017 at 22:38The Dual bank mechanism works by switching internal flash banks while code address stays the same. How to extend this mechanism to two external QSPI flashes operating in XIP mode? Is gating QSPI chip select using ...
Posted on January 24, 2018 at 21:07Should be MCKDIV.Also, the same typo is in the relevant .svd files, making thus MCJDIV appear as xCR1 bitfield name in debuggers (spotted in https://community.st.com/thread/46652-f446-documentation-saispdif-tx-bit-...
Posted on March 04, 2018 at 11:18I tried to transplant the mbedtls ssl server code for stm32f769i discovery board to stm32f746g discovery board. The error was printed on to the lcd. I.E. the headers are changed and the BSP is changed. The error is f...
Posted on December 01, 2017 at 17:55References:STM32L0x3 - RM0367, Rev 5STM32L0x2 - RM0376, Rev 4In both cases, the description of ADC sampling time register (ADC_SMPR) says,Bits 2:0 SMP[2:0]: Sampling time selectionThese bits are written by softwar...
Posted on March 27, 2015 at 18:35When I configure the ADC sampling time using SMP[2:0] of the ADC_SMPR register, the resulting conversion time (1.5 cycles + sampling time) does not match what I expect. RM0367, v2, section 14.13.6 lists the followi...
Posted on January 10, 2017 at 06:53&sharp1RM0367 Rev.5, Ch. 6.1.6 Dynamic voltage scaling configuration requires toPoll VOSF bit of in PWR_CSR. ait until it is reset to 0.twice. The note at the end of the same chapter says,During voltage scaling co...
Posted on June 29, 2017 at 00:14Hi. I use Keil Compiler and HAL lib. I configure TIM4 as normal timer (time base counter) and implement Update event with HAL_TIM_PeriodElapsedCallback function. My initialization code below;__HAL_RCC_TIM4_CLK_ENABLE(...
