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Posted on July 09, 2018 at 15:06I'm having trouble entering stop2 -- instead of going to stop2 my code seems to enter sleep; this is based upon measuring power levels -- I have the RTC fed by an external crystal and a 1 second interval alarm. I can...
Posted on October 10, 2016 at 13:12Hello, should i connect 3V battery to Vss or Vssa for RTC backup (external 32768 resonator)? #too-vague #stm32-vbat-rtc
Posted on July 09, 2018 at 14:24 Hi, The MCU is STM32F4 I put the Timer2 (60MHz clock) to trigger every 100mS. it means it triggers its interrupt and ADC every 100mS. Below is the configuration of the ADC and Timer2. I checked the TIM2 interr...
Posted on July 10, 2018 at 18:35I have tracked down another oversight using CubeMX to generate FatFs code for STM32H743i_Eval. In the STM32Cube\Repository\STM32Cube_FW_H7_V1.2.0\Projects\STM32H743I_EVAL\Applications\FatFs\FatFs_uSD_DMA_RTOS I found...
Posted on July 07, 2018 at 01:39Trying to figure out reasons why a CubeMX build cannot replicate the functionality of the repo application:STM32Cube\Repository\STM32Cube_FW_H7_V1.2.0\Projects\STM32H743I_EVAL\Applications\FatFs\FatFs_uSD_DMA_RTOS.The...
Posted on December 02, 2017 at 22:01Is it just me, or is the STM32CubeH7 missing the low-layer API? I can't seem to select LL instead of HAL on the individual drivers in STM32CubeMX under settings like I can on STM32F7 cube projects. In the descri...
Posted on July 09, 2018 at 16:46 The original post was too long to process during our migration. Please click on the attachment to read the original post.
Posted on July 06, 2018 at 15:50Hello,we are running a stm32f49xxx mcu with sdram which is used as a video ram.now with higher product lines we have more traffic on the memory bus causing flickering. With code optimization we can reduce it but it ap...
Posted on June 25, 2018 at 15:37Hi,How can I tell for sure if a microcontroller supports Field Oriented Control for BLDC motors? I am particularly interested in STM32F303VC and STM32L4R7VI.The STM32F303VC for sure does that because I remember readin...
Posted on July 11, 2018 at 12:02Hello,in the L4+ series, DMA2D, OCTOSPI, SDMCC, SPI and USART have a Version register at offset 0x3F4 of the IP address space, as seen in the current header files. RM0432 Rev.3 does not mention and describe these regi...
