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MCU: STM32F777Cube: 4.25.0FW: v1.11.0I'm seeing cases where the F7's SDMMC isn't setting any of the required Status Register bits as the result ofan R1 response to a READ_SINGLE_BLOCK command after having previously handled up to tens of thousands of...
Hi AllCan anyone suggest the example code for Spi interfacing between STM32L151QD and External flash memory.,Through my STM32L151QD I want to read and write from External flash memory , The both STM32 and Flash memory is connected with SPI interface
I saw the web https://community.st.com/s/article/FAQ-DMA-is-not-working-on-STM32H7-devices,and I change the ram address.uart can transmit with DMA but can`t receive.and the spi can`t transmit with dma.
Hello everybody!A short questen: I crashed the uC on the STM3240G_EVAL,so is there a On-Top Board what fit on the Connectors CN1 ... CN2 ?.. Also a board to switch fast the microcontroller ..I searched for it, but didn't find such a board.Thanks, Dir...
Hey everyone,In my last application I had a DMA double buffer moving data from a peripheral to memory, it would fll one buffer, inform the cpu and while it filled the second buffer, the first buffer would be sent to the sdcard.I want to do the same t...
We wanted to use the uart2 serial port of STM32F072CBT6. We used the STM32CUBE tool to generate the code, but the debugging found that we could not enter the interrupt of uart2.We had no problem setting uart1 and uart3 to use before.The initializati...
I have an app that uses SPI5 on an F7 chip with no problems, but it no longer works when I upgraded to the H7 chip (at the same time I changed to using SPI2).I am no longer getting the serial clock signal (SPI_SCK) on SPI2 on the H7 chip.I defined SP...
With the data cache enabled is the backup ram cached such that an Invalidate Cache instruction is required to write the data through?
This is a minor thing, but.... STM32L433xx/STM32L443xx Errata sheet, ES0318, revision 4, section 2.1.2 on VDIV/VSQRT says there are two work possible arounds, but then lists the same work around 2 times (disable lazy FPU context save). What is the ...
I'm using a Nucleo-H743ZI and have configured ADC3 to trigger off of TIM3. It is scanning 4 channels every 10 us. I also have BDMA configured for the ADC. The ADC end-of-scan interrupt is occurring every 10 us, but the DMA interrupt is only occurr...
