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HSE clock hardware design clarification

Hello everyone,I am designing a board using STM32L496RE and I'm currently in the HSE clock design phase.I have chosen a 16MHz crystal with CL 18pF. I have been following the AN2867 (https://www.st.com/content/ccc/resource/technical/document/applicati...

CProt by Associate
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TIM_ETR_SetConfig() static or not?

Hello,when generating a STM32CubeMX project from within Keil µVision, in stm32f4xx_hal_tim.c (STM32F4xx_DFP/2.13.0) the function TIM_ETR_SetConfig is defined as static in the .c file and none-static in the corresponding .h file, so i need to change t...

TBirk by Associate
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STM32L151RC GPIO BRR register missing?

Hi,to clear bit 7 in port C I used a write to the BRR register: GPIOC->BRR = 0x00000080. Did not clear bit 7. A write to BSRR works: GPIOC->BSRR = 0x00800000. Is the BRR register not implemented (seems kind of redundant anyway with having BSRR)...

hugo1 by Associate II
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STM32L073 system information block address map

I trying to find information on the system information block of the stm32l073rb, specifically the address of the vrefint calibration value. I've looked in the ref manual, the data sheet and the L0 HAL docs and have come up empty. Please show me how s...

ETone by Associate III
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STM32f405 clock synchronize

Hello, I'm trying to use two identical stm32f4 boards to synchronize tick of one with respect to other.I'm using can to using can protocol for communication in Interrupt mode.So the Master is supposed to be always running and the slave when powers up...