Ask questions on STM32CubeMX. Discuss code generation and configuration challenges, among other topics.
We are pleased to announce that the version 6.15.0 of STM32CubeMX is available. What is new in 6.15.0: Enhanced microprocessor support: Added the STM32MP21-A35-TD, STM32MP21-M33-TD, STM32MP25-M33-TD, and STM32MP23-M33-TD trusted domains for the STM32...
I install STM32CubeMX Ver 6.11.1. The page does not load when I log in to the accountThis prevents the firmware package from being downloaded
Using Nucleo 32H723ZG board, would like to add WolfSSL to it Working on an SSH server app.Using the LwIP_HTTP_Server_Socket_RTOS example... watching this video:https://youtu.be/pUd2HEfBp3w?si=jiB2MysS9unIuVDr&t=1727It appears that my problem is this...
How to start with FileX using CubeMX?In CubeMX I enabled ThreadX and FileX with the default configuration, increased ThreadX "memory pool size" to 2k and enabled "Generate Init Code" for both.In app_azure_rtos.c, tx_application_define() function MX_...
Hi, I create a new project with STM32CubeIde 1.15.1 (but same with 1.10.1)I add SDRAM 1 - BANK 1When I debug this project, after HAL_SDRAM_Init function in MX_FMC_Init(), I can wath the memory in MEMORY BROWSER at address 0x60000000.But on reference ...
Hello,I'm working on a CMake F030 based project, generated with STM32CubeMX (MX and firmware package up to date to last version)So the CMakeList.txt link to a stm32cubemx library. Generating the basic project is ok. But now, I have created a libPWM t...
Dear All, In my project, I am using STM32F405RG MCU for file read/wirte operations using FATFS.I declare the physicaldrive as USB DEVICE (Mass storage Class) ,while I am generating a code for USB DEVICE(Mass Storage Class) its only works for...
Hi, I am frequently getting tired while working with the STM32H743ZIT6 144-pin Nucleo board / STM32H743IIT6 controller board and an externally connected Ethernet module using a communication protocol. Despite trying many different ways, it is still n...
Using STM32CubeMX 6.3.0 with a dual core STM32H755 micro I have a dip switch I wish to be able to read from both cores. Some peripherals (like TIM1 for example) have check boxes for runtime contexts that let you check M7 and M4 to access the peripher...
I would like to know if there is a way to NOT enable interrupts during the initialization of the EXTI. See below for snippet /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI0_IRQn, 0, 0); HAL_NVIC_EnableIRQ(EXTI0_IRQn); HAL_NVIC_SetPriorit...
