STM32CubeMX (MCUs)

Ask questions on STM32CubeMX. Discuss code generation and configuration challenges, among other topics.

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STM32CubeMX 6.15.0 released

We are pleased to announce that the version 6.15.0 of STM32CubeMX is available. What is new in 6.15.0: Enhanced microprocessor support: Added the STM32MP21-A35-TD, STM32MP21-M33-TD, STM32MP25-M33-TD, and STM32MP23-M33-TD trusted domains for the STM32...

Trouble changing timebase to something other than systick

I have a NUCLEO-H745ZI-Q and am trying to teach myself how to use FreeRTOS on it. I can't figure out how to change the HAL timebase away from systick to one of the other timers, as is strongly recommended for FreeRTOS use. I start a new STM32 proje...

MMcPh.1 by Associate II
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  • 5 replies
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STM32CubeIDE and STM32CubeMx bugs on Mac Catalina

These two bugs seem related. Bug 1 on STM32CubeIDE. After modifying an ioc file, when you regenerate, the IDE wipes all the contents of the Drivers folder and all subfolders, and doesn't replace them! Yow.Bug2 on STM32CubeMx. When generating code, th...

AVoel.1 by Associate III
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  • 2 replies
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SystemClock_Config code generated using HAL is working fine but using LL API it is failing for STM32F072xb. is that something missed in code generation. Attached the code generated by both LL and HAL.

Code generated using LL : (Issue)------------------------------------------void SystemClock_Config(void){ LL_FLASH_SetLatency(LL_FLASH_LATENCY_0); if(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_0) { Error_Handler();  } LL_RCC_HSI_Enable();  /* Wait til...

MAnna by Associate
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  • 1 replies
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Resolved! CubeMX Generate wrong code for I2S Master-Transmit, or F302 has bug? (CubeMX ver 1.4.2 + STM32Cube_FW_F3_V1.11.1 + STM32F302R8)

Dear Experts,I ported I2S RX and TX program from F401 to F302R8 Nucleo board. And I encountered **unexpected** phenomenon.When I use I2S for receiving data (Half-duplex, Master-Receive mode, 48kHz, 24bit data on 32bit frame), it works fine. That mean...

KAJIK.1 by Associate III
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  • 2 replies
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CubeMX doesn't allow Fadc > 18 MHz for H743 Rev. V

If from the "Clock Configuration" tab Fadc > 36Mhz then the Clock prescaler for the ADC is automatically set to /2 where the /1 is diabled. For > 72MHz it is /4 where /1 and /2 are disabled. Rev. 2 has an additional /2 divider that has been taken int...

Wde G.1 by Associate II
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  • 1 replies
  • 0 kudos