How do I configure all of the timers to 216 MHz on the stm32f767zi?

[JStay.1]

I have a Nucelo-F767ZI development board and am having difficulties configuring all of the timers to run at 216 MHz using the CubeMX tool.

According to the data sheet of the STM32F767xx, on page 38 all of the timers have a max clock speed of 216 MHz. Per the footnote on Table 6, the TIMPRE bit of the RCC_DCKCFGR register controls if some of these timers (specifically Timer 2) can run at either 108 or 216 MHz.

I have confirmed I can get Timer 1 to run at 216 MHz. When attempting to configure Timer 2 to run in the same manner, I observe half the rate (of the PWM signal configured).

This is all using mostly the HAL API and Clock Configuration in CubeMX. In the Clock Configuration, by changing HCLK to 216 MHz, APB2 runs at 216 MHz but APB1 runs at 108 MHz. This seems to explain my observations. I can't get the configuration to provide a solution to get both APB1 and APB2 to run at 216 MHz. In addition, and mostly due to my ignorance, I don't know which control is tied to the aforementioned TIMPRE bit. The reference manual suggests this is a timer prescaler control, but I see two timer prescalers (at least what I think APB1 and APB2 Prescaler might be).

I have attached two images. The first is the working clock configuration that solves successfully. The second, is my attempt to get both timers to run at 216 MHz, but an error is highlighted for PCLK1.

[Tesla DeLorean]

Yes, because you can't make the APB1 BUS CLOCK that fast.

What you need to do is change the peripheral clock plumbing to the TIMx, and that is done via the "Peripheral Clocking", such that the TIMCLK is derived from HCLK/SYSCLK

From RM0410

2. When TIMPRE bit of the RCC_DCKCFGR1 register is reset, if APBx prescaler is 1, then TIMxCLK = PCLKx, otherwise

TIMxCLK = 2x PCLKx.

3. When TIMPRE bit in the RCC_DCKCFGR1 register is set, if APBx prescaler is 1,2 or 4, then TIMxCLK = HCLK, otherwise

TIMxCLK = 4x PCLKx.

/**
  * @brief  Initializes the RCC extended peripherals clocks according to the specified
  *         parameters in the RCC_PeriphCLKInitTypeDef.
  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
  *         contains the configuration information for the Extended Peripherals
  *         clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).
  *
  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
  *         the RTC clock source; in this case the Backup domain will be reset in
  *         order to modify the RTC Clock source, as consequence RTC registers (including
  *         the backup registers) are set to their reset values.
  *
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
..
  /*------------------------------------ TIM configuration --------------------------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
  {
    /* Check the parameters */
    assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
 
    /* Configure Timer Prescaler */
    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
  }

/** @brief  Macro to configure the Timers clocks prescalers
  * @param  __PRESC__  specifies the Timers clocks prescalers selection
  *         This parameter can be one of the following values:
  *            @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
  *                 equal to HPRE if PPREx is corresponding to division by 1 or 2,
  *                 else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
  *                 division by 4 or more.
  *            @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
  *                 equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
  *                 else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
  *                 to division by 8 or more.
  */
#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\
                                                 RCC->DCKCFGR1 |= (__PRESC__);           \
                                                }while(0) 

[TDK]

ignore