STM32CubeIDE (MCUs)

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STM32CubeIDE 1.16.1 released

STM32CubeIDE 1.16.1 was released on st.com as well as an in-tool update patch aligned with STM32CubeMX v6.12.1 that is available for download. Main issues fixed in this minor release: Fixed issue when install OpenSTLinux MP2 plugin from OpenSTLinux r...

STM32CubeIDE 1.16.0 released

STM32CubeIDE 1.16.0 was released today on st.com as well as an in-tool update patch. What is new in 1.16.0?Microcontroller and board lists aligned with STM32CubeMX v6.12.0 : STM32C0, STM32WB0 and STM32MP25XXAdded CMake support for multicontext projec...

Resolved! hi2c2 in an external .c

Hello to all.I'm coding an I2C comunication and the IDE (1.4.0) create the Private variable I2C_HandleTypeDef hi2c2; and then the function MX_I2C2_Init. Everithing ok.I'm using an external .c file to handle the I2C communication and how can I access ...

MSole.1 by Associate
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Resolved! STM32CubeIDE 1.5.0 crash issue

Hi,I cannot import existing project into Workspace. Here's the error log when I try to select a root directory: eclipse.buildId=Version 1.5.0 java.version=1.8.0_272 java.vendor=AdoptOpenJDK BootLoader constants: OS=linux, ARCH=x86_64, WS=gtk, NL=en_...

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Gaston by Senior
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Resolved! How to write dirctly to a Flash memory address?

Hi, I'm working on Stm32CUBE IDE with STM32LO71RB. I would like to write a version number when I am flashing my device at EEPROM Flash memory address 0x08080000. I've tried HAL_FLASH_Program(), but I have to execute it at each reset. I would like to...

RChar.2 by Associate II
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Resolved! I can't debug my own board

Thank you for helping.environment:IDE: STM32CubeIDE Ver1.3.0Board: Self-made boardDebugger: STLink V3-MINII connected to debug the board I made this time with IDE.The situation is different from that of the evaluation board.The following message is o...

Ebun.1 by Senior
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Resolved! Dual core H7 debugging problem in CubeIDE

I have a problem with launching both cores in STM32H745 in CubeIDE.I've set that configuration:connect under reset for CM7, with halt all coresCross Trigger Interface (CTI) , allow other cores to halt this core and signal halts events to other cores ...

DBrau.2 by Associate III
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