Can someone with internal knowledge confirm that the LIS3DSH in I2C mode never drives the SCL line low and that a standard "single master push-pull SCL" can be used in combination with the bidirectional SDA line.
The LIS3DSH datasheet contains the following text (not very clear):"If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW, to force the transmitter into a wait state....