Sorry for all the postings, but we're under a deadline and really struggling with the reliability of the LSM6DS3.Here's another of the strange things we're seeing on the LSM6DS3: It just stops driving DRDY on INT1. Since our present design relies on ...

I'm seeing some very odd behavior on the LSM6DS3. It works "most" of the time, but seems to randomly change its own settings from time to time. Before we get into that, though, I'd like to ask about the timing of INT1 when driven by the DRDY signal.I...

The LSM6DS3 has two "reboot" style operations. I've read spec sheets and appnotes but can't find a clear description of one of them.BOOT (CTRL3_C bit 7) appears to freshly load the "trimming parameters", which I presume are factory values written to ...

The spec sheet contradicts itself on this question. What does the chip actually expect/do?SPI is an "big endian" protocol at the bit level, where the MSb of each byte is transmitted first on the wire and the LSb of each byte is transmitted last. Look...

We're designing the LSM6DS3 into an existing product that already uses a 2V5 supply rail. The LSM6DS3's spec sheet says that running it at 2V5 is well within spec, but all of the examples refer to a 1V8 supply. Is there any reason that a 2V5 supply i...