Resolved! I'm using the LIS3DH. Do I need to provide a 90 mS delay between configuration of CTRL_REG1 and reading the OUT registers or the FIFO to insure stable output ?
I'm using the LIS3DH. The Application Note AN3308 specifies a 90 mS delay time between configuration and reading data in the suggested procedure for performing a self test, (p57 of DocID18198 Rev 3). The delay is, "... for stable output". Once ODR i...