[BUG] STM32 HAL ETH driver sets wrong MDIO frequency
The code in HAL_ETH_SetMDIOClockRange() function for H7 series, starting from HCLK frequency of 150 MHz and higher, sets the MDIO clock divider to 102. Per IEEE 802.3 specification the MDIO clock must not exceed 2,5 MHz, which means that it will be v...