STM32G431K8 SVD file seems wrong. Reference manual (RM0440, February 2024 RM0440 Rev show EXTI->PR1 bits PIF29,PIF30,PIF31 (Comparator 3,4,5 outputs). Fresch SVD file (STM32G4 SVD V2.2) missing these bits.
It seems that STM32H563MI has four I2C ( I2C1 ~ I2C4):However, the corresponding STM32H563.svd only includes 2 I2C ( I2C1 ~ I2C2).https://stm32-rs.github.io/stm32-rs/STM32H563.html
I am working with STM32G474RET6U MCU and I would like to check the values of bit filed EXTSEL (ADCx->CFGR.EXTSEL) the problem is that according to SFR view this bit field starts on 6th bit of CFR register, but according to the reference manual it sho...
Hi,I have STM32L0x1 svd v1.3, and it seems the PWR_CR LPSDSR bit is missing.Is there a more recent svd file? I can't seem to find it.Thanks
I have the STM32H73x.svd from then STMCubeH7 pack version 1.9.0 but it is far from compete/correct.Some examplesAHB3 clock enable /reset registers do not have any of the OCTOSPI items in there, but has a QSPI entry.Similar some timer enables/reset ar...
No GPIOx registers are present in System Viewer for STM32G051 or STM32G061 microcontrollers during debug session. There are 12 different .sfr files for each different variant of STM32G0 microcontroller, but only the above two lack GPIO registers in S...
Hello everyone!I have just noticed that The OPAMP_CSR_OPARANGE bit in NUCLEO-U575ZI-Q is not shown during debug mode. Some bug perhaps?..
Specifically the SNB (SSN1 & SSN2 in the data sheet) bits are defined erroneously as being 3 bits wide at position 6, whereas it should be 7 bits wide, allowing all 128 sectors in each bank to be erased.#define FLASH_CR_SNB_Pos (6...
SVD version 1.2, vs RM0468 Rev 3RCC PLLxDIVR has errorsRCC->PLL2DIVR, DIVN1 should be DIVN2RCC->PLL2DIVR, DIVP1 should be DIVP2RCC->PLL2DIVR, DIVQ1 should be DIVQ2RCC->PLL2DIVR, DIVR1 should be DIVR2