About CGran.3

CGran.3 · 2021-11-03

I have the STM32H73x.svd from then STMCubeH7 pack version 1.9.0 but it is far from compete/correct.Some examplesAHB3 clock enable /reset registers do not have any of the OCTOSPI items in there, but has a QSPI entry.Similar some timer enables/reset ar...

CGran.3 · 2021-07-09

Like a few others on the STM32H7 line I as seeing some weird behavior with ACTVODSRDY.This happens with both the demo projects and my own code.Sometimes when I power up this board ACTVODSRDY = 1and PWR control register 3 (PWR_CR3) is in the expected ...

CGran.3 · 2021-11-04

@Mike_ST Thanks,It appears the Delay Block Bypass (DLYBYP) is also missing for the OCTOSPI DCR1 Register and the DCR4 register is of the incorrect length for the refresh field. (16 vs 32 bits)

CGran.3 · 2021-11-04

@Mike_ST I pulled down a few different sources and looked in that location as well. All instances seem to be the same and missing data. I was hoping not to have to edit them myself to get them up to date.

CGran.3 · 2021-11-04

Kraal,This is the one I am using, however it has multiple errors in it as mentioned above, and probably others that I have not found yet. I was hoping there was one that had been 100% validated against the RM somewhere.

CGran.3 · 2021-11-04

@Mike_ST Can you also put a ticket in to get the enable/reset registers fixed. Specifically the AHB3 ones for OCTOSPI and APB1 for the Timer 23 and 24?

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Is there a complete/correct STM32H73x.svd file anywhere?

ACTVODSRDY STM32H735G-DK Question

Re: Is there a complete/correct STM32H73x.svd file anywhere?

Re: Is there a complete/correct STM32H73x.svd file anywhere?

Re: Is there a complete/correct STM32H73x.svd file anywhere?

Re: Is there a complete/correct STM32H73x.svd file anywhere?