STM32H7A3 flash CR register incorrectly defined in SVD and source

[SFren.5]

Specifically the SNB (SSN1 & SSN2 in the data sheet) bits are defined erroneously as being 3 bits wide at position 6, whereas it should be 7 bits wide, allowing all 128 sectors in each bank to be erased.

#define FLASH_CR_SNB_Pos                     (6U)
#define FLASH_CR_SNB_Msk                     (0x7FUL << FLASH_CR_SNB_Pos)      /*!< 0x00001FC0 */
#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */
#define FLASH_CR_SNB_0                       (0x01UL << FLASH_CR_SNB_Pos)      /*!< 0x00000040 */
#define FLASH_CR_SNB_1                       (0x02UL << FLASH_CR_SNB_Pos)      /*!< 0x00000080 */
#define FLASH_CR_SNB_2                       (0x04UL << FLASH_CR_SNB_Pos)      /*!< 0x00000100 */
#define FLASH_CR_SNB_3                       (0x08UL << FLASH_CR_SNB_Pos)      /*!< 0x00000200 */
#define FLASH_CR_SNB_4                       (0x10UL << FLASH_CR_SNB_Pos)      /*!< 0x00000400 */
#define FLASH_CR_SNB_5                       (0x20UL << FLASH_CR_SNB_Pos)      /*!< 0x00000800 */
#define FLASH_CR_SNB_6                       (0x40UL << FLASH_CR_SNB_Pos)      /*!< 0x00001000 */

This causes the HAL_FLASHEx_Erase to behave improperly.

The SVD is being used by the STM32-RS project and is causing incorrect code generation.

[KDJEM.1]

Hi @Community member​ and welcome to the Community 🙂,

Thank you for bringing this issue to our attention.

I confirm the issue: The FLASH_CR1 and FLASH_CR2 registers are wrongly described in the svd file.

I reported this issue internally.

Internal ticket number: 135971 (This is an internal tracking number and is not accessible or usable by customers).

When your question is answered, please close this topic by choosing Select as Best. This will help other users find that answer faster.

Thank you

Kaouthar

[SFren.5]

The SR register is also incorrect:

Bit 22 does not exist

Bit 28 CRCRDERR is missing

[KDJEM.1]

Hi @Community member​ ,

I confirm this issue.

I have passed this internally for correction.

Thank you for your contribution.

Kaouthar