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SFren.5
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2022-10-03
2023-06-14
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STM32H7A3 flash CR register incorrectly defined in SVD and source
2022-10-03
Specifically the SNB (SSN1 & SSN2 in the data sheet) bits are defined erroneously as being 3 bits wide at position 6, whereas it should be 7 bits wide, allowing all 128 sectors in each bank to be erased.#define FLASH_CR_SNB_Pos (6...
Re: STM32H7A3 flash CR register incorrectly defined in SVD and source
2022-10-03
The SR register is also incorrect:Bit 22 does not existBit 28 CRCRDERR is missing
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