STM32 MCUs Embedded software

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STM32G4 Errata 2.7.9 ADC trigger sequencing

ES0430 - Rev 8 - March 20232.7.9 An ADC instance may impact the accuracy of another ADC instance at specific conditionsHas anyone implemented this item listed in the Errata sheet for STM32G4 series for ADC section? It asks for:Ensure that conversions...

mitk by Associate II
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How to use external SDRAM as an data memory?

I am using STM32H747I-DISCO board where the stack and heap memory allocated in SRAM , but I want to use external SDRAM as stack and heap memory, can any one please help me how to configure  external SDRAM as main data memory instead of SRAM.

How to use SDRAM for bss and data region?

I am using STM32H747I-DISCO board, I want to use external SDRAM for bss and data region and I called the SDRAM initialization function inside the SystemInit() function and I tried with the debugger point it will go to hard fault when debugger point h...

USBX CDC ACM on STM32F767 Nucleo board not working

I have spent over a week trying to get the USBX CDC ACM virtual com port to work on a STM32F7 family nucleo-144 board. I'm using an STM32F767 as a representative processor. I've tried multiple examples and approaches with no success.  The device enum...

tec683 by Associate III
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RTC seems to be always enabled - hard fault

Hi,  I got a Nucleo F103RB, and I am running the very same software I run on my Nucleo F7ZI, and I am getting this weird hard fault that always. I do not enable RTC, but right before the fault happens, the ICSR register tells there is a pending inter...

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lwip intermediate link down handling

Hi together,after working more deeply into the link status register handling of Ethernet PHYs i did notice that the Link Status bit in the Basic Status Register (BSR) is Latched Low. That is also the reason why we need to read it twice. The ST driver...

PhilippH by Associate II
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