Ask questions and find answers on STM32 hardware set-ups, including schematic-related challenges, debugging probes, power configurations, and more.
Starting server with the following options: Persistent Mode : Disabled Logging Level : 1 Listen Port Number : 61234 Status Refresh Delay : 15s Verbose Mode : Disabled SWD Debug : Enabled InitWhile...
Hello, Could anybody please look at the circuit, and if it is correct.I am not sure if C5 is necessary to be there.Thank you.
I fired up CubeIDE again after a while, it updated from v1.4 or so to 1.8 now.When I was about to debug, it offered to update the firmware of my ST-Link V3 SET.It claimed that was successful.When I then wanted to debug, it claims there is no target.I...
Hello,For a project, I created a PCB with an STM32F411 using a 10pin JTAG port for SWD programming.I tried to connect my card using the ST LINK V2 box and the ST Link utility software but I get the following error:The st link works because I can prog...
Maybe is a hardware problem since the microcontroller is on a custom board I designed. The problem is the following: The microcontroller only runs the program the moment I load the code, if I reset it or power up the board after a power-off it does n...
I'm trying to understand the benefits/tradeoffs of the "Direct SMPS supply" and "SMPS supplies LDO" options for the STM327H (red and blue options in the attached figure). Since the LDO adds an extra source of power loss, and the SMPS can supply all d...
Hello everyoneI'm using a Nucleo board, specifically the L031K6. I'm used to sending UART messages from the board to the PC via the ST-Link USB interface. In this project I wanted to do the other direction going from the PC up to the card over the sa...
The STM32F407 is programmed with STMCube IDE and there is no error during initizalition of the functions; HAL_Init(), SystemClock_Init(); MX_USB_DEVICE_Init().As I expect that virtual com port will be opened while the PCB is plugged into my PC, unfor...
Hi all, I design PCB with STM32F767 in LQFP144 package. I know that design guidelines suggested adding a decoupling capacitor on each VDD pin but by layout (tracks density) I don't have space for capacitors on each VDD pin (elements on only one side ...