SVD file of the STM32H753 seems erronous compared to the stm32h753xx.h.
The DFSDM section 29.7 channel configuration register has an offset for each channel of 0x20*y while the SVD file has a 0x4 offset between the channels. Can somebody state the correct offset? SVD: ... <name>DFSDM_CHCFG0R1</name> <displayName...