Hi,I tried to set the read protection to level 1 (the one where we should be able to wipe out everything) .But after that i can't get no connection anymore with STM32IDE , ST-link or any tool. Connection is completely broke.Before changing this level...
The board can be populated with a Quad SPI PSRAM, sharing OCTOSPI1. Do I need to remove the OctoSPI before using the Quad SPI or is it enough to disconned CS?
How I understand from this schematics: PC8 and PD2 have pull-up resistors connected to them while the rest of them don't, this means that the rest should get Pull-up resistor in the settings of the GPIO and this will enable the pull-up resistor from ...
Hi,we have a PHY with several bootstraps. Some of them are shared with the RMII from a STM32H753 (see image below, controller is on the left).A FreeRTOS+TCP network stack is used, which, when rebooted, first does some low level inits with HAL_ETH_Ini...
Hello,We working on custom board. We using this controller STM32745IIkx. In JTAG we connect the USART1 port, but there is pin mapping issue, so I am unable to use USART1.So instead of UASART1 can I use USART2.I am sharing its schematic THE VCP_TX and...
Starting server with the following options: Persistent Mode : Disabled Logging Level : 1 Listen Port Number : 61234 Status Refresh Delay : 15s Verbose Mode : Disabled SWD Debug : Enabled InitWhile...
Hello, Could anybody please look at the circuit, and if it is correct.I am not sure if C5 is necessary to be there.Thank you.
Hi, I'm working on a custom board which I've been programming with an ST-LINK V2 using the SWCLK and SWDIO lines. I mistakenly left BOOT0 floating, but I need to order more boards, so I'm going to correct this mistake.My question: Am I right in think...
I fired up CubeIDE again after a while, it updated from v1.4 or so to 1.8 now.When I was about to debug, it offered to update the firmware of my ST-Link V3 SET.It claimed that was successful.When I then wanted to debug, it claims there is no target.I...