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Undocumented Pullup on Pin PB4/JNRST

Hi,as I see it here in my test PCB, the pin PB4 (JNRST for JTAG interface) seems to have an internal weak pullup during reset (I assume 40kOhm as NRST - an external 10kOhm will pull this pin down, but 100kOhm pull down does NOT work...).It is luckily...

flyer31 by Senior
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Hello. I am building an application and planning on using the STLINK-V3SET to program and debug, but I can not find any reference which describes what pins to connect for the VCP_TX and RX pins from the programming header to the MCU.

I believe that I connect the following:T_SWDIO -> PA13T_SWCLK -> PA14T_NRST -> NRSTBut which pins on the MCU do I connect for the virtual comport? VCP_TX -> PA2 or PA9VCP_RX -> PA3 or PA10Also, SWO is not avaliable on the Cortex M0+? so is not conne...

gmassey by Associate
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