When I try to set up a HAL_UART_Receive_IT my program won't compile.I am new to the FreeRTOS concept, but it is necessary for me to learn how to set it up for a project I am working on. For that, I started restructuring a previous project to learn fr...
I am trying to setup FreeRTOS for the new STM32N6 Nucleo board. Running into the following error `GCC/ARM_CM55_NTZ/non_secure/port.c:1814: undefined reference to `__privileged_sram_start__'`.Based on https://github.com/STMicroelectronics/x-cube-freer...
I generally want to support both static/auto/dhcp in software config. This is most easily done by changing LWIP.c Around line 62: /* IP addresses initialization with DHCP (IPv4) */ ipaddr.addr = gstate.ipaddr; // NOT 0 netmask.addr = gstate.netmask...
Moved from the Feedback ForumHi,1. Referring to below link, can we use this for STM32L562ZET6Q part without any change.2. What changes are to be done to make use of USART3 (PC10,PC11) rather USART1 (PA9,PA10). How to use the ST Open Bootloader for ST...
We are performing SPI communication using DMA.In this case, we manually set the GPIO to High/Low as SPI_CS, but (obviously) SPI_CS goes High before all of the SPI CLK is sent.How can we manually return SPI_CS to its original state after all of the SP...
Fairly basic question; When working with CubeMX, I want to set up ADC1 and ADC2 to trigger and sample at the same time, using an HRtimer trigger pulse, at about 5 MSPS. ADC1 is sampling channel 1, and ADC2 is sampling channel 4.I have them working ri...
Please tell me how to add HID to STM32 USB-Audio to enable Next Track etc.
Hello ST community,I have a question regarding the HID functionality of an STM32 controller.I have realised a (driverless!) joystick with an STM32 controller. So far everything works fine.However, I would like to write additional PC software that can...
There are some errors in SVD when it comes to reset values. I'm basing my judgement as I am comparing SVD with RM0492: RCC_AHB1ENR SVD: 0xd0000100 RM:0x90000100 (BKPRAMEN set in SVD)RCC_AHB2ENR SVD:0xc0000000 RM:0x40000000 (resered bits b31 set in ...
ADC_CFGR register and EXTSEL field.In SVD this single field is split among four 1-bit long ones (according to RM0492) and enumerated values desciptions are messed up (adc_ext_trg0 & adc_ext_trg1 repeated for all 4 "subfields")RM0492 discusses this as...
