Hi Everyone! I am trying to understand why I cannot get the result of the AES in GCM mode HAL_CRYP_Encrypt on the F439ZI board to match the AES in GCM result anywhere else. I am using Python's pycryptodome library for result comparison. I have previ...
Hello ST Community,Can we apply Secure Boot on the STM32C031 family? I didn't find anything on the documentation. If not, what are the product series where we can apply Secure Boot?Thank you.
Hello,I'm willing to use the SBSFU in order to securely update the firmware on a custom board using an STM32G0 MCU.The example used in the MOOC with the simpleAPP is confusing, using the script to patch SBSFU with user code was straightforward and wi...
Hi, I am going through the firmware protection hands on in Part 4 of the STM32 Security MOOCs located here :https://www.youtube.com/watch?v=RahlfYJ1gDs&list=PLnMKNibPkDnF0wt-ZI74SflnsBV4yKzkO&index=5&t=782sThe instructor in this hands on asks to spec...
HW: NUCLEO-H563ZIHello, can someone explain the following behavior to me? Is this a bug or am I using the HAL incorrectly?Thanks a lot. Code snippetThe resultThe result is correct, but the behavior is strange. I receive two error callbacks also.First...
Flash Memory is divided in different zones Secure (also protected by watermark), NCS and NS. All of such zone are defined in the the partition_stm32U575xx.h and SAU is enabled.MCU is in secure mode and want to write in the non secure area.Erasing ret...
Good day!I am working with the STM32H753 product. I am trying to understand the sequences and state machines for RSS activation. The reference manual (RM0433) does not provide enough information to grasp the full picture. Additionally, there are no e...
I am Missing the Option Security>RNG in my the .ioc tool. Does the F446RE does not have a RNG?i experience identical problems to Implementation of ECC on STM32f446 (Page 1) — wolfSSL — wolfSSL - Embedded SSL Library
Hi,When trying to run a simple TrustZone+UART project generated by STM32CubeMX, the chip raises a HardFault when switching to NonSecure mode. In the HardFault handler, the Cortex-M33 CFSR registrer is set to 0x400, indicating an instruction bus error...
Hello,We have a cybersecurity requirement to protect against unauthorized firmware uploads during data load operations or shop load using JTAG. Is there a feature available in the STM32F7xxx family Microcontroller that complies with cybersecurity sta...