Decoupling & Vcc Pin Configuration for STM32 MCUs

[Chubs]

Hello Community,

Reaching out to you for feedback on the attached configuration for Vcc on my new STM32 based DAQ board.

My objective was to reduce the inductance to the Vcc pins of the MCU (STM32G0B0RET6 64 LQFP package). Hence I clubbed three pins:

A) VBAT

B) VREF+

C) VCC

Altogether & decoupled them as attached in the following layout. Now it makes sense to do this, however are there any obvious aspects that I might've missed here? Your insights would be invaluable!

Optimized Decoupling Layout for STM32G0B0RET6

Power Supply Scheme for STM32G0B0RET6

I plan to use the ADC on board in some future cases, apart from that mostly everything is 

[STOne-32]

Dear @Chubs ,

It looks for me a very good design from the Power decoupling ( which is a single pair + VBAT+VREF) .  I have two small remarks :

1) I assume LSE and 32,768KHz Crystal is it used . If yes Ok . If no to see how the change the PCB for its caps to be very close to PC14,PC14.

2) if you will use ADC in future , all depends on your precision ,  when VREF+ is connected to VDD - Digital power - take care when doing sampling with ADC to not have huge I/O toggling or sudden increase of current to keep stable conversion - tied to VREF+ value after calibration.  But is fine .

Ciao

STOne-32

[Chubs]

Hello @STOne-32,

Kindly guide more.

My assumption being:

1. No matter how I connect Vref+ Pin - we only have one 3.3V supply which is Vdd on board

2. Vref Int shall be used for ADC reference - which is assumed to be stable irrespective of the variations on the Vdd

Kindly guide further on these assumptions, as this could end up rendering entire board useless if we do not do this correctly.

Looking forward for more community feedback.