Ask questions and find answers on STM32 microprocessors, including hardware, power, DRAM, flashing, interfacing, device tree, and peripherals.
Hi All,i want to use ES8388 audio coec with STM32MP157. All hardware connections are tested, ad i can see MCLK on scope, also codec is visible on I2C bus.But i'm facing dificulties with Device Tree configuration. snippet from my dts file :sound { ...
Hello, ST CommunityI have successfully implemented dB meter code on my STM32L4 Discovery kit and got SPL in dB, But the code has .a file made by ST.I want to implement dBSPL meter in STM32MP1 using PDM sensor. Can it support same .a file on MP1 boar...
Hello,I'm trying to add a python GTK application I created to the startup using systemd.In order to do so I created the following gatewayservice.service file:[Unit] Description=Gateway service Requires=graphical.target After=graphical.target [Servi...
Hello , New year 2021 Greetings:party_popper: ! Hope you all are doing great !Looking at the FreeRTOS wiki , there is no support for Cortex - A7?Is there an alternate port available for FreeRTOS for Cortex A7? or some customization for the same?what ...
Hello ST Community,I was following below link,https://wiki.st.com/stm32mpu/wiki/How_to_integrate_AWS_IoT_Greengrass_on_top_of_openSTLinux_distribution#cite_note-3I found that I have to buy STPM4RasPI extension board.The board is not available on mous...
Hi STI have a question when setting the ADC Clock on the M4 Core side.The STM32MP151C datasheet states that the ADC Clock can be set up to 36Mhz.When the AHB clock is 200Mhz, what clock will it work with if I set "ADC ClockPrescaler" to "ADC_CLOCK_SY...
what does MPU_InitStruct.TypeExtField ? mean only three options available #define MPU_TEX_LEVEL0 ((uint8_t)0x00)#define MPU_TEX_LEVEL1 ((uint8_t)0x01)#define MPU_TEX_LEVEL2 ((uint8_t)0x02)does it mean only 3 set of HAL_MPU_ConfigRegion(&MPU_InitSt...
We have own MP157 based module and it sometimes hangs after NRST during debug. It doesn't respond to JTAG DAP, further NRST pulses doesn't help but NRST_CORE helps. It seems as errata "Incorrect reset of glitch-free kernel clock switch". We tried sw ...
dts:in M4:I find the SPI1 doesn't work.
