STM32 MPUs Products

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Resolved! Purpose of board ID field in OTP

Hello,U-Boot has an stboard command that writes a board ID into OTP (word 59 on STM32MP15x lines, word 60 on 13x lines).TF-A displays this board ID if a device tree label "board_id" is present in the bsec node.Could you please explain the purpose of ...

STM32MP157C kernel 6.1 nand not working

I have developed a custom stm32mp157c board with a nand IC as storage using the FMC peripheral. This has worked fine with kernel v5.15, but I am trying to upgrade to kernel v6.1 due to driver related issues of the ethernet switch. However I can't see...

SLitt.1 by Associate
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Resolved! Information regarding the USBH from reference manual

Hi     I am working on a custom board based on STM32MP157A . For USBH_EHCI while checking the register (USBH_EHCI_INSNREG05) mentioned in the reference manual (RM0436) it was mentioned to refer to UTMI specification. could you please suggest / share ...

UTMI_snip.PNG

Re: STM32MP1 FDCAN issues

I am setting up the fd-can protocol on stm32mp1, please let me know after creating the dts file from stm32mx , how to transfer that file to stm32mp1 to use, do I use the command root@stm32mp1:~# ls / sys/class/netend0 lo usb0 , it doesn't show that t...

Resolved! FDCAN can not start, no clock found

after follow the wiki, the can0(m_can2) can not start up on stm32mp157d-dk1root@stm32mp1:~# dmesg | grep can[ 0.384348] can: controller area network core[ 0.384666] can: raw protocol[ 0.384678] can: broadcast manager protocol[ 0.384695] can: netlink ...

Huibean by Associate II
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Resolved! EMMC boot in place of SD card in STM32mp135

I am using emmc in place of SD-card for custom hardware of STM32MP135FAE7. If FlashLayout_sdcard_stm32mp135f-dk-optee.tsv file will work using STM32cube programmer to upload all boot files??Whether all procedure will be same for boot sequence as we d...

Resolved! STM32MP151C SPI5 clock much slower

I am trying to configure SPI5 on STM32MP151C where MPU is a master and ESP32C6 is a slave. The clock used in the device tree is HSI 64MHz. SPI driver is running with 2MHz configured and divisor in the SPI_CFG1 register is correctly set to 32. In the ...

vsaakian by Associate III
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