STM32 MPUs Products and hardware related

CMake does not use proper linux interpreter library

Hello, I am doing a little bit of cross compiling but I have a problem with the linux interpreter. I am using the openstlinux-weston distro with the ld-linux-armhf.so.3 but the binaries after coming out of my cross compilation are using ld-linux.so.3...

How to set THREAD_VERSION for ot-br-posix

Hello,I wants to bitbake ot-br-posix with OT_THREAD_VERSION=1.1, Modified the ot-br-posix_git.bb file, add -DOT_THREAD_VERSION=1.1 in this file. But result is ot-br-posix using Thread Version 1.2Does somebody know how to solve this issueMany thanks...

STM32MPU ecosystem release V4.1.0 is online !

STM32MPU ecosystem release V4.1.0 is online !Dear STM32 MPU Community, We are please to announce that New MP1 Ecosystem V4.1.0 is available.It contains :openstlinux-5.15-yocto-kirkstone-mp1-v22.11.23 - UpdatedSTM32CubeMP1-v1.6.0STM32CubeIDE-v1.11.0 -...

Building and Deploying OP-TEE for 1st Time.

Hello,while building OP-TEE I encountered one error:Set the ROOT directory " export FIP_DEPLOYDIR_ROOT=$PWD/../../FIP_artifacts"make -f $PWD/../Makefile.sdk CFG_EMBED_DTB_SOURCE_FILE=stm32mp157a-dk1 allERROR:make[1]: Entering directory /developer-pac...

Hi, i am using stm32mp157c in my product.so when the CAN interrupt is invoked after that the Button Interrupt stop working.both device tree nodes are following.

GPIO for button is 98.GPIO for CAN is 92.In dts file,button: gpio-keys {        compatible = "gpio-keys";        #address-cells = <1>;        #size-cells = <0>;        status = "okay";        button1: plugin-gpio {            label = "plugin-gpio";  ...

Hi , we are using STM32MP157 and want to enable the USB1 port for connecting the peripheral. Can i get some reference on this ??, there are lot of reference for USB2 OTG port but could find much on USB (ehci) port 1.

STM32MP1 read SRAM3 memory on A7 core

Hi!I am using STM32MP157C-DK2 board and I want to share memory between to processor. My idea is to update variable in the M4 core and then read it in the A7 core (linux). To do this, I create a section in SRAM3 (both cores can access) and save the va...