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How to make Ethernet and lwIP working on STM32

Chief II

This is an umbrella topic where I will collect the key problems and solutions to finally get networking on STM32 working. The issues formatted as bold are the most critical ones.

HAL ETH drivers have been significantly reworked since the following firmware packages: CubeF4 v1.27.0, CubeF7 v1.17.0, CubeH5 v1.0.0, CubeH7 v1.10.0

Series: F1, F2, F4, F7, H5, H7 (all STM32 with Ethernet)

Series: F1, F2, F4, F7 (older Synopsys basic peripheral)

Series: H5, H7 (newer Synopsys QoS peripheral)

Series: F7, H7 (Cortex-M7 CPU)

lwIP API related:

Other related information:

Another detailed topic by @alister​: "[bug fixes] STM32H7 Ethernet". While mostly dedicated to H7 series, it also has a good amount of information relevant to all Ethernet/lwIP related development.

Open source zero-copy Ethernet/lwIP driver example. The hardware driver is for F2 series, which means that it's almost the same for all Fx series. The lwIP related code and general ideas are still valid for all series.

My other closely related topic: "Actually working STM32 Ethernet and lwIP demonstration firmware". As that topic is currently unavailable, because ST still has not moved it to the new forum, I am attaching a PDF copy of that topic and the related firmware files to this topic.

Chief II

As the main topic has hit a 10000 character limit, I'm changing this message to a list of fixed issues, which many people will still find useful.

Series: F1, F2, F4, F7 (older Synopsys basic peripheral)

Series: H7 (newer Synopsys QoS peripheral)

Series: F7, H7 (Cortex-M7 based)

  • lwIP driver Rx data buffers not aligned to cache line size. The address and size of buffers, on which D-cache invalidation is done, must be aligned to __SCB_DCACHE_LINE_SIZE, which is 32 bytes for Cortex-M7. Instead of doing D-cache maintenance, newer ST provided code uses MPU to configure specific memory regions as non-cacheable. It's a very poor solution performance wise, but at least it is functionally correct. For a proper and decent solution it is recommended to read my article "Maintaining CPU data cache coherence for DMA buffers". [Fixed by using MPU.]
ST Employee

Hi @Piranha​ ,

Needed follow-up actions for each discussion are tracked internally by me & Imen.

I suggest to close the current question.


To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

Chief II

I've added substantial amount of new information.

Hi Piranha,

Thank you very much for the information.

If I may please ask why you don't share the sources ? I will try to do the modifications for H7.


nguen nguyen
Associate II

Can anyone send example project ? thanks so much Cubemx 5.4


My fixes and improvements to ST's STM32H7 ETH driver and lwIP ethernetif.c are at

Source code and documentation attached.

I don't use evaluation boards or build example code.

You'll have to port my changes yourself.


Thank you @Piranha​ for this detailed write-up! I've updated the original thread to point to this one. *excellent* information and lots of detail.

Associate III

I am attempting to get Ethernet work on an STM32H745 on the M7 core currently. But I am using CubeIDE 1.4.2 and CubeMX 6.0.1 with ver 1.8.0 of the H7 firmware package. Since these are a bit newer, it is unclear to me which of these issues are still present and which still need fixing. Does anyone have any updates that apply to the newer stuff?

Yes, I think same as you. It is worthy to make it clear which ones have remained until now.