Ethernet reference clock affecting ADC values in STM32 microcontrollers
In various STM32 microcontroller applications, the Ethernet reference clock (ETH_REF_CLK) has been observed to introduce noise into ADC (analog-to-digital converter) measurements. This article explores the problem, its manifestations, and potential solutions to mitigate its impact.
1. Problem description
The issue primarily arises in STM32 microcontrollers where the Ethernet reference clock operates at high frequencies, such as 50 MHz. This high-speed clock can interfere with the ADC's performance, leading to increased noise in the ADC readings.
The problem is particularly pronounced in microcontrollers like the STM32F7xx and STM32F437, STM32H5, and STM32H7 series as well where the ADC pins are located close to the oscillator and RMII_CLK pins.
2. Examples
In this section, we provide a detailed example of the issue as well as some occurrences across some impacted STM32 series.
Below is an example of the noise that we observe with ADC on an STM32F7 when ADC is connected to ground and to VDD with 12b resolution respectively. This is induced by the phy clock input of the Ethernet peripheral:
3. Occurrences of the issue
3.1. STM32F7xx microcontroller
- Configuration: The microcontroller uses an LQFP144 package, with ADC pins on the 1-36 pin side, which is also where the quartz and RMII_CLK are mapped.
- Issue: This configuration leads to additional noise (approximately 10 LSB with peak regions at 500 Hz) on pins 36 (ADC123_IN2) and 37 (ADC123_IN3), despite the presence of an antialiasing filter.
- Observation: The noise is significantly higher compared to other similar filtered sensor signals, which exhibit around 5 LSB noise.
3.2. STM32F437 microcontroller
- Configuration: The microcontroller uses an LQFP100 package, measurement on ADC1_IN0 (PA0).
- Issue: The 50 MHz RMII clock (PA1) affects the measurement on ADC1_IN0 (PA0), causing noise levels of approximately 100 codes in 4096.
- Observation: When the ETH_REF_CLK is removed, the noise level drops to around 10 codes in 4096, similar to other ADC channels.
3.3. NUCLEO-F756ZG board
- Configuration: The board runs at 216 MHz with APB2 at 13.5 MHz. The ADC is configured with a 12-bit resolution and a sample time of 480 cycles.
- Issue: The ADC and DMA function correctly, but the signal is very noisy, even with the input shorted to AGND or connected to AVDD.
- Observation: Various attempts to smooth the signal, such as using a high-quality potentiometer and resistors, did not significantly reduce the noise.
3.4. NUCLEO-H743ZI2 board
- Configuration: NUCLEO-H743ZI2 board with a 16-bit ADC. The Ethernet clock is outputting the 50 MHz clock.
- Issue: The actual dynamic range of the ADC is low, with significant noise observed even when the ADC input is directly connected to ground.
- Observation: The 16-bit ADC appears to provide less than 10 bits of true resolution due to the noise.
4. Proposed solutions
Several solutions can be proposed to mitigate the impact of the Ethernet reference clock on ADC performance:
4.1. Oversampling technique
- Suggestion: Use oversampling to reduce noise, although this will reduce the sampling rate.
- Observation: Oversampling can help average out the noise, but it may not be suitable for applications requiring high sampling rates.
4.2. Lower resolution
- Suggestion: Use a lower resolution (for example, 12-bit) to reduce the impact of noise.
- Observation: Lowering the resolution can decrease noise on an absolute count basis.
4.3. Proper PCB routing
- Suggestion: Ensure proper PCB routing of high-speed clocks, including shielding and impedance matching, to reduce noise.
- Observation: Proper PCB design can significantly mitigate noise issues.
4.4. Switching to MII mode
- Suggestion: Switch from RMII mode to MII mode, where the clock frequencies are lower (25 MHz), resulting in less noise.
- Observation: This approach can reduce noise but may introduce other issues, such as MII availability.
4.5. Reallocate the ADC channels
- Suggestion: Avoid using the ADC channels too close to the RMII clock.
- Observation: This approach can reduce noise but limits the number of ADC channels available.
Conclusion
The interference of the Ethernet reference clock with ADC measurements in STM32 microcontrollers could be visible across a range of products when combining their usage. Its affect can vary depending on the package and mode used for booth Ethernet and ADC.
By implementing the proposed solutions: oversampling, lowering resolution, ensuring proper PCB routing, and switching to MII mode, the impact of this noise can be significantly reduced. These solutions can help achieve more accurate and reliable ADC readings in applications involving high-speed Ethernet clocks.
My research on nucleo-H743zi2 shows that problem is not 50 MHz clock itself, but Ethernet IC:
Pictures demonstrate spikes on Vdd = 3.3V power line.
This affects not only ADCs, but DACs as well via V-Reference.
Spikes on voltage rail are always there, I mean on my nucleo-H743 Ethernet was not configured, all jumpers associated with Ethernet were Removed as described in UM2407.
The solution is to cut power to IC: LAN8742a de-soldering L1 inductor, completely shouting down Ethernet feature .
For new design, I'd suggest install another 3.3V LDO exclusively for powering Ethernet sub-module. Basically, "split" power domains between main uCPU and Ethernet.
