| Function |
Series/Lines |
Doc Reference - Revision |
Description |
Date of added update |
| SPI |
STM32F427xx
STM32F437xx
STM32F429xx
STM32F439xx
|
ES0206 Rev20
(Feb 2024)
|
Add section:
Corrupted last bit of data and/or CRC, received in Master mode with delayed SCK feedback
Description
When performing a receive transaction in I2S or SPI Master mode, the last bit of the transacted frame is not captured when the signal provided by an internal feedback loop from the SCK pin exceeds a critical delay. The lastly transacted bit of the stored data then keeps the value from the pattern received previously. As a consequence, the last receive data bit may be wrong, and/or the CRCERR flag can be unduly asserted in the SPI mode if any data under checksum, and/or just the CRC pattern is wrongly captured. In SPI mode, data are synchronous with the APB clock. A delay of up to two APB clock periods can thus be tolerated for the internal feedback delay. The I2S mode is more sensitive than the SPI mode, especially in the case where an odd I2S prescaler factor is set and the APB clock is the system clock divided by two. In this case, the internal feedback delay is lower than 1.5 APB clock period. The main factors contributing to the delay increase are low VDD level, high temperature, high SCK pin capacitive load, and low SCK I/O output speed. The SPI communication speed has no impact.
Workaround
The following workarounds can be adopted, jointly or individually:
• Decrease the APB clock speed.
• Configure the I/O pad of the SCK pin to be faster.
The following table gives the maximum allowable APB frequency (that still prevents the issue from occurring) versus GPIOx_OSPEEDR output speed for the SCK pin, with a 30 pF capacitive load.
|
Mar 2024
|
| System |
STM32L451xx
|
ES0387 Rev10
(Oct 2023)
|
Update section:
Corrupted content of the backup domain due to a missed power-on reset after this domain supply voltage drop
Description
The backup domain reset may be missed upon a power-on following a power-off, if its supply voltage drops during the power-off phase hitting a window, which is few mV wide before it starts to rise again. In this critical window, the flip-flops are no longer able to safely retain the information and the backup domain reset has not yet been triggered. This window is located in the range between 100 mV and 700 mV, with the exact position depending mainly on the device and on the temperature. This missed reset results in unpredictable values of the backup domain registers. This may cause a spurious behavior (such as driving the LSCO output pin on PA2 or influencing backup functions).
Workaround
Apply one of the following measures:
• In the application, let the VDD and VBAT supply voltages fall to a level below 100 mV for more than 200 ms before a new power‑on.
• If the above workaround cannot be applied, and the boot follows a power‑on reset, erase the backup domain by software.
When the application is using shutdown mode, user needs to discriminate between the power‑on reset or an exit from a shutdown mode.
For this purpose, at least one backup register must have been previously programmed with a BKP_REG_VAL value with 16 bits set and 16 bits cleared.
Robustness of this workaround can be significantly improved by using a CRC rather than registers. The registers are subject to backup domain reset.
The workaround consists of calculating the CRC of the backup registers: RCC_BDCR and RTC registers, excluding bits modified by HW.
The CRC result can be stored in the backup register instead of a fixed value. This value needs to be updated for each modification of values covered by CRC, such as by using CRC peripheral.
At the very beginning of the boot code, insert the following software sequence:
1. Check the BORRSTF flag of the RCC_CSR register. If set, the reset is caused by a power on, or is exiting from shutdown mode.
2. If BORRSTF flag is true, and the shutdown mode is used in the application, check that the backup register value is different from BKP_REG_VAL. When tamper detection is enabled, check that no tamper flag is set. If both conditions are met then the reset is caused by a power-on.
3. If the reset is caused by a power-on, apply the following sequence:
a. Enable the PWR clock in the RCC, by setting the PWREN bit.
b. Enable the backup domain access in the PWR, by setting the DBP bit.
c. Reset the backup domain, by:
i. Writing 0x0001 0000 in the RCC_BDCR register, which sets the BDRST bit and clears other register bits that might not be reset.
ii. reading the RCC_BDCR register, to make the reset time long enough
iii. writing 0x0000 0000 in the RCC_BDCR register, to clear the BDRST bit
d. Clear the BORRSTF flag by setting the RMVF bit of the RCC_CSR register.
|
Mar 2024
|
|
STM32L452xx
|
ES0388 Rev10
(Oct 2023)
|
|
STM32L462CE
STM32L462RE
STM32L462VE
|
ES0389 Rev10
(Oct 2023)
|
|
STM32L05xxx STM32L06xxx
|
ES0251 Rev5
(Dec 2021)
|
Add section:
LSE crystal oscillator may be disturbed by transitions on PC13
Description
On LQFP and UFQFPN packages, the LSE crystal oscillator clock frequency can be incorrect when PC13 is toggling in input or output (for example when used for RTC_OUT1).
The external clock input (LSE bypass) is not impacted by this limitation.
The WLCSP and UFBGA packages are not impacted by this limitation.
Workaround
None.
Avoid toggling PC13 when LSE is used on LQFP and UFQFPN packages.
|
Jun 2024
|
| STM32L07xxx STM32L08xxx |
ES0292 Rev7
(Mar 2022)
|
|
STM32L031xx
STM32L041xx
|
ES0322 Rev4 (Dec 2021) |
|
STM32L011xx
STM32L021xx
|
ES0332 Rev5 (Feb 2022) |
| STM32L010xx |
ES0483 Rev2 (Dec 2021) |
STM32H562xx
STM32H563xx
STM32H573xx |
ES0565 Rev4 (Nov 2023) |
Add section:
LSE crystal oscillator may be disturbed by transitions on PC13
Description
On LQFP and VFQFPN packages, the LSE crystal oscillator clock frequency can be incorrect when PC13 is toggling in input or output (for example when used for RTC_OUT1).
The external clock input (LSE bypass) is not impacted by this limitation.
The WLCSP and UFBGA packages are not impacted by this limitation.
Workaround
None.
Avoid toggling PC13 when LSE is used on LQFP and VFQFPN packages.
|
Jun 2024
|
| STM32L05xxx STM32L06xxx |
ES0251 Rev5
(Dec 2021)
|
Add section:
Wakeup sequence from Standby mode when using more than one wakeup source
Description
The various wakeup sources are logically OR-ed in front of the rising-edge detector which generates the wakeup
flag (WUF). The WUF flag needs to be cleared prior to the Standby mode entry, otherwise the MCU wakes up
immediately.
If one of the configured wakeup sources is kept high during the clearing of WUF flag (by setting the CWUF bit), it may mask further wakeup events on the input of the edge detector. As a consequence, the MCU could not be able to wake up from Standby mode.
Workaround
To avoid this problem, the following sequence should be applied before entering Standby mode:
1. Disable all used wakeup sources.
2. Clear all related wakeup flags.
3. Re-enable all used wakeup sources.
4. Enter Standby mode.
Be aware that, when applying this workaround, if one of the wakeup sources is still kept high, the MCU enters the
Standby mode, but then it wakes up immediately generating the power reset.
|
Jun 2024
|
| STM32L07xxx STM32L08xxx |
ES0292 Rev7
(Mar 2022)
|
|
STM32L031xx
STM32L041xx
|
ES0322 Rev4 (Dec 2021) |
|
STM32L011xx
STM32L021xx
|
ES0332 Rev5 (Feb 2022) |
| STM32L010xx |
ES0483 Rev2 (Dec 2021) |
STM32H562xx
STM32H563xx
STM32H573xx |
ES0565 Rev4 (Nov 2023) |
Add section:
Ethernet active clock in sleep mode control is missing
Description
üEthernet RX clock enable in sleep mode (ETHRXLPEN bit in RCC_AHB1LPENR register) can be disabled if ETHTXEN bit in RCC_AHB1ENR register and ETHTXLPEN bit in RCC_AHB1LPENR register are not set. ETHRXLPEN=1 has no control on Ethernet RX clock enable in sleep mode.
Workaround
If RX clock is needed in sleep mode, keep ETHTXEN=1 in RCC_AHB1ENR register and ETHTXLPEN=1 in RCC_AHB1LPENR register.
|
Jun 2024
|
| GPIO |
STM32L05xxx STM32L06xxx |
ES0251 Rev5
(Dec 2021)
|
Add section:
GPIO locking mechanism failed if critical address is read.
Description
GPIO locking sequence requires predefined steps of writing and reading operations over GPIOx_LCKR register. Reading from address (SRAM/Flash/peripherals) which 10 lsb bits corresponds to GPIOx_LCKR address (0x5000 XX1C) is interpreted by GPIO locking state machine as dummy read from GPIOx_LCKR register. GPIO locking sequence will fail if there is inserted this additional dummy read from GPIOx_LCKR register (reset of the locking sequence). The GPIO locking state machine is sensitive only to reading done by CPU (not by DMA).
Workaround
GPIO locking sequence code must not use variables stored at SRAM addresses which 10 lsb bits correspond to 0x01C (each 1kB is critical address). Avoid using variables on the stack (because critical address can be present on the stack area) in locking sequence code. Disable interrupts during the GPIO locking sequence because interrupt service routine can perform reading from critical address. Locking sequence routine must be placed in memory section outside critical addresses.
Recommended code for GPIO locking sequence is below. It uses only register access with disabled interrupts in critical code part. The correct code placement (outside critical addresses) is solved here by repeating the locking sequence in case of error – then at least one locking code will be at correct placement (linker independent solution).
Locking mechanism code example
/* (1) Save interrupts enable state */
/* (2) Disable interrupts */
/* (3) Write LCKK bit to 1 and set the pin bits to lock */
/* (4) Write LCKK bit to 0 and set the pin bits to lock */
/* (5) Write LCKK bit to 1 and set the pin bits to lock */
/* (6) Restore interrupts enable state */
/* (7) Read the Lock register */
/* (8) Check the Lock register for lock (in case of error perform lock second time) */register uint32_t tmp1; /* place critical variable into register to not use SRAM */
register uint32_t tmp2; /* place critical variable into register to not use SRAM */
uint32_t irqenabled;
tmp1 = GPIO_Pin;
tmp2 = GPIO_LCKR_LCKK | GPIO_Pin;
...
irqenabled = __get_PRIMASK(); /* (1) */ /* remember interrupts enable state */
__disable_irq(); /* (2) */
GPIOA->LCKR = tmp2; /* (3) */
GPIOA->LCKR = tmp1; /* (4) */
GPIOA->LCKR = tmp2; /* (5) */
if (!irqenabled) __enable_irq(); /* (6) */
GPIOA->LCKR; /* (7) */
if ((GPIOA->LCKR & GPIO_LCKR_LCKK) == 0) /* (8) */ /* check if locking failed */
{
__disable_irq(); /* (2) */
GPIOA->LCKR = tmp2; /* (3) */
GPIOA->LCKR = tmp1; /* (4) */
GPIOA->LCKR = tmp2; /* (5) */
if (!irqenabled) __enable_irq(); /* (6) */
GPIOA->LCKR; /* (7) */
if ((GPIOA->LCKR & GPIO_LCKR_LCKK) == 0) /* (8) */
{
/* Manage error – optional */
}
}
|
Jun 2024
|
| STM32L07xxx STM32L08xxx |
ES0292 Rev7
(Mar 2022)
|
|
STM32L031xx
STM32L041xx
|
ES0322 Rev4 (Dec 2021) |
|
STM32L011xx
STM32L021xx
|
ES0332 Rev5 (Feb 2022) |
| STM32L010xx |
ES0483 Rev2 (Dec 2021) |
| IWDG |
STM32F100x4 STM32F100x6
STM32F100x8 STM32F100xB
|
ES093 Rev8
(Jul 2022)
|
Remove sections:
Delete duplicated sections:
- RVU flag not cleared at low APB clock frequency
- PVU flag not cleared at low APB clock frequency
|
Mar
2024
|
|
STM32F10xx4 STM32F10xx6
|
ES0348 Rev10
(Jun 2022)
|
|
STM32F101xF
STM32F101xG STM32F103xF
STM32F103xG
|
ES0346 Rev7
(Jul 2022)
|
|
STM32F101xC
STM32F101xD
STM32F101xE
STM32F103xC
STM32F103xD
STM32F103xE
|
ES0340 Rev17
(Jun 2022)
|
|
STM32F105xx STM32F107xx
|
ES022 Rev11
(Jun 2022)
|
STM32F100xC
STM32F100xD STM32F100xE |
ES0136 Rev7
(Aug 2022)
|
| FMC/FSMC |
STM32F469xx STM32F479xx
|
ES0321 Rev11
(Apr 2024)
|
Add section:
CTB1, CTB2, MODE[2:0] bitfields in FMC_SDCMR are write-only.
Description
CTB1, CTB2, MODE[2:0] bitfields in FMC_SDCMR are write-only, and always read as zero.
|
Apr 2024
|
|
STM32F446xC
STM32F446xE
|
ES0298 Rev6
(Apr 2024)
|
|
STM32F412xE STM32F412xG
|
ES0305 Rev13
(Jan 2024)
|
|
STM32F74xxx STM32F75xxx
|
ES0290 Rev7
(Jul 2019)
|
|
STM32F76xxx STM32F77xxx
|
ES0334 Rev9
(Dec 2022)
|
|
STM32F72xxx STM32F73xxx
|
ES0360 Rev5
(Feb 2020)
|
|
STM32L496xx STM32L4A6xx
|
ES0335 Rev18
(Feb 2024)
|
|
STM32H745xx STM32H747xx
STM32H755xx STM32H757xx
|
ES0445 Rev4
(Dec 2023)
|
Add section:
Inaccurate LSE frequency in oscillator bypass mode in combination with VBAT mode
Description:
When LSE is used in bypass mode (RCC_BDCR. LSEBYP = 1), and if the microcontroller switches to VBAT mode, LSE frequency is not accurate in VBAT mode if external clock VLSE_ext max voltage is higher than min (VBOR0, VBAT).
Workaround:
If application requires accurate LSE frequency in oscillator bypass mode and in combination with VBAT mode, VLSE_ext max voltage must be lower than min (VBOR0, VBAT).
|
Jul 2024
|
| DAC |
STM32H562xx
STM32H563xx
STM32H573xx |
ES0565 Rev4 (Nov 2023) |
Add section:
Invalid DAC output voltage for several DAC kernel clocks
Description:
The DAC output voltage might be incorrect when DAC kernel clock is different from HCLK (ADCDACSEL[2:0] bits equal to 000 in RCC_CCIPR5 register) or SYSCLK (ADCDACSEL[2:0] bits equal to 001 in RCC_CCIPR5 register).
Workaround:
When DAC is used, use ADCDACSEL[2:0] = 000 or 001 in RCC_CCIPR5 register.
|
Jun 2024
|
| LPTIM |
Add section:
LPTIM2_CH1 might prevent system from entering low-power modes
Description:
When LPTIM2_CH1 output is enabled, it might lead to wake-up interrupt request from EXTI input event 49, as the default value for IMR49 bit in EXTI_IMR2 register is equal to 1 (EXTI interrupt input 49 is unmasked). Consequently, it might prevent system from entering low-power modes.
Workaround:
When LPTIM2_CH1 output is enabled, and system needs to enter low-power mode mask EXTI interrupt input 49 by setting IMR49 bit in EXTI_IMR2 register to 0.
|
Jun 2024
|
