STM32 MCU errata sheets: Expected preliminary updates

[KDJEM.1]

Introduction

This article includes preliminary updates of STM32 MCU errata sheets reported since 1st January 2024. It highlights the current description requiring update and the expected one if available.

The purpose of this article is to deliver any expected updates to our MCU errata sheets prior to actual documentation releases. We wish to be transparent with our updates and provide them as fast as possible, to assist you in your design process.
This article is updated on a monthly basis. Once these preliminary updates are manifested in the errata sheets, this article is refreshed with new information.
Moving forward, we are also working on providing errata sheet releases on a more frequent basis.

IMPORTANT NOTICE - READ CAREFULLY:

• STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to this article at any time without notice.
• Information in this article supersedes and replaces information previously supplied in any prior versions of this article.

• The following table gives a quick reference to the preliminary documentation updates which may be changed or improved without notice.
• This article will be reviewed on a monthly basis and applied updates will be removed from the table.
• The hyperlinks under "Doc Reference - Revision" provides a direct link to the specific document page where the description is located.

Summary of documentation updates: "STM32 MCU errata sheets"

Function	Series/Lines	Doc Reference - Revision	Description	Date of added update
SPI	STM32F427xx STM32F437xx STM32F429xx STM32F439xx	ES0206 Rev20 (Feb 2024)	Add section:  Corrupted last bit of data and/or CRC, received in Master mode with delayed SCK feedback Description When performing a receive transaction in I2S or SPI Master mode, the last bit of the transacted frame is not captured when the signal provided by an internal feedback loop from the SCK pin exceeds a critical delay. The lastly transacted bit of the stored data then keeps the value from the pattern received previously. As a consequence, the last receive data bit may be wrong, and/or the CRCERR flag can be unduly asserted in the SPI mode if any data under checksum, and/or just the CRC pattern is wrongly captured. In SPI mode, data are synchronous with the APB clock. A delay of up to two APB clock periods can thus be tolerated for the internal feedback delay. The I2S mode is more sensitive than the SPI mode, especially in the case where an odd I2S prescaler factor is set and the APB clock is the system clock divided by two. In this case, the internal feedback delay is lower than 1.5 APB clock period. The main factors contributing to the delay increase are low VDD level, high temperature, high SCK pin capacitive load, and low SCK I/O output speed. The SPI communication speed has no impact. Workaround The following workarounds can be adopted, jointly or individually: • Decrease the APB clock speed. • Configure the I/O pad of the SCK pin to be faster. The following table gives the maximum allowable APB frequency (that still prevents the issue from occurring) versus GPIOx_OSPEEDR output speed for the SCK pin, with a 30 pF capacitive load.	Mar 2024
System	STM32L451xx	ES0387 Rev10 (Oct 2023)	Update section: Corrupted content of the backup domain due to a missed power-on reset after this domain supply voltage drop Description The backup domain reset may be missed upon a power-on following a power-off, if its supply voltage drops during the power-off phase hitting a window, which is few mV wide before it starts to rise again. In this critical window, the flip-flops are no longer able to safely retain the information and the backup domain reset has not yet been triggered. This window is located in the range between 100 mV and 700 mV, with the exact position depending mainly on the device and on the temperature. This missed reset results in unpredictable values of the backup domain registers. This may cause a spurious behavior (such as driving the LSCO output pin on PA2 or influencing backup functions). Workaround Apply one of the following measures: • In the application, let the VDD and VBAT supply voltages fall to a level below 100 mV for more than 200 ms before a new power‑on. • If the above workaround cannot be applied, and the boot follows a power‑on reset, erase the backup domain by software. When the application is using shutdown mode, user needs to discriminate between the power‑on reset or an exit from a shutdown mode. For this purpose, at least one backup register must have been previously programmed with a BKP_REG_VAL value with 16 bits set and 16 bits cleared. Robustness of this workaround can be significantly improved by using a CRC rather than registers. The registers are subject to backup domain reset. The workaround consists of calculating the CRC of the backup registers: RCC_BDCR and RTC registers, excluding bits modified by HW. The CRC result can be stored in the backup register instead of a fixed value. This value needs to be updated for each modification of values covered by CRC, such as by using CRC peripheral. At the very beginning of the boot code, insert the following software sequence: 1. Check the BORRSTF flag of the RCC_CSR register. If set, the reset is caused by a power on, or is exiting from shutdown mode. 2. If BORRSTF flag is true, and the shutdown mode is used in the application, check that the backup register value is different from BKP_REG_VAL. When tamper detection is enabled, check that no tamper flag is set. If both conditions are met then the reset is caused by a power-on. 3. If the reset is caused by a power-on, apply the following sequence: a. Enable the PWR clock in the RCC, by setting the PWREN bit. b. Enable the backup domain access in the PWR, by setting the DBP bit. c. Reset the backup domain, by: i. Writing 0x0001 0000 in the RCC_BDCR register, which sets the BDRST bit and clears other register bits that might not be reset. ii. reading the RCC_BDCR register, to make the reset time long enough iii. writing 0x0000 0000 in the RCC_BDCR register, to clear the BDRST bit d. Clear the BORRSTF flag by setting the RMVF bit of the RCC_CSR register.	Mar 2024
	STM32L452xx	ES0388 Rev10 (Oct 2023)
	STM32L462CE STM32L462RE STM32L462VE	ES0389 Rev10 (Oct 2023)
	STM32WBA5x	ES0592 Rev4 (June 2024)	Add section: When the HSE32 clock is stopped for a time between 2 and 5ms, it may need a longer delay to stabilize (tstab) when restarting Description  When the HSE32 is restarted, after having been off within a window between 2 ms to 5 ms, the HSE32 clock may be not ready after HSERDY = 1. If the HSE32 is restarted too early there may be consequences like a CPU hard fault, wrong time counting in timers, or other peripherals that use the HSE32 clock may be impacted. Applications where HSE32 could be stopped for more than 2ms and less than 5ms must use the workaround. The maximum HSE32 oscillator stabilization time tSTAB is increased to 1 ms. (typical 360 µs). Workaround Before stopping the HSE clock, the following peripherals (when using HSE clock) shall deselect the HSE as kernel clock: SYSCLK in SW PLL1 in PLL1SRC RTC and TAMP in RTCSEL ADC4 in ADCSEL 2.4 GHz RADIO sleep clock in RADIOSTSEL. 2.4 GHz RADIO baseband kernel clock shall be disabled in BBCLKEN. When re-enabling the HSE clock and before reusing the clock for SYSCLK, PLL1, RTC, TAMP, ADC4, 2.4 GHz RADIO sleep clock, and 2.4 GHz RADIO baseband clock, software shall add an additional time of 200 µs after HSERDY = 1. The HSE clock security shall not be used, kept disabled, in HSECSSON. Even with this work around, 2.4 GHz RADIO instances may occasionally be skipped causing a missed packet (when tstab is longer than 360us and max 1ms). To prevent this the 2.4 GHz RADIO wakeup can be advanced by 600 µs.	Oct 2024
			Add section: Fast-mode Plus can’t be activated using SYSCFG_CFGR1 Description  Activating Fast-mode Plus mode for GPIO PB3, PA15, PA7 or PA6 by setting the corresponding bits in register SYSCFG_CFGR1 does not take effect. Workaround None.
			Add section: ICACHE fails after STOP1 Description If ICACHE was not retained the contents is uncertain and can lead to a wrong cache hit. Workaround Retain ICACHE or force the invalidation when coming out of STOP1.
			Add section: No security gating is applied to MCO on PA8 with AF0. Description When GPIO are configured as Alternative Function 0 (AF0), the MCO is output on PA8. Setting Bit SYSCLKSEC in register RCC_SECCFGR does not make this output secure. MCO will always be output. Workaround None.
TAMP	STM32WBA5x	ES0592 Rev4 (June 2024)	Add section: TAMP active tamper prescaler extension ATCKSEL[3] is not supported. Description TAMP active tamper prescaler extension ATCKSEL[3] is not supported. Functionality associated with value 0xB is not supported. Workaround  None	Oct 2024
IWDG	STM32F100x4 STM32F100x6 STM32F100x8 STM32F100xB	ES093 Rev8 (Jul 2022)	Remove sections: Delete duplicated sections: - RVU flag not cleared at low APB clock frequency - PVU flag not cleared at low APB clock frequency	Mar 2024
	STM32F10xx4 STM32F10xx6	ES0348 Rev10 (Jun 2022)
	STM32F101xF STM32F101xG STM32F103xF STM32F103xG	ES0346 Rev7 (Jul 2022)
	STM32F101xC STM32F101xD STM32F101xE STM32F103xC STM32F103xD STM32F103xE	ES0340 Rev17 (Jun 2022)
	STM32F105xx STM32F107xx	ES022 Rev11 (Jun 2022)
	STM32F100xC STM32F100xD STM32F100xE	ES0136 Rev7 (Aug 2022)
FMC/ FSMC	STM32F469xx  STM32F479xx	ES0321 Rev11 (Apr 2024)	Add section: CTB1, CTB2, MODE[2:0] bitfields in FMC_SDCMR are write-only. Description  CTB1, CTB2, MODE[2:0] bitfields in FMC_SDCMR are write-only, and always read as zero.	Apr 2024
	STM32F446xC STM32F446xE	ES0298 Rev6 (Apr 2024)
	STM32F412xE STM32F412xG	ES0305 Rev13 (Jan 2024)
	STM32F74xxx  STM32F75xxx	ES0290 Rev7 (Jul 2019)
	STM32F76xxx STM32F77xxx	ES0334 Rev9 (Dec 2022)
	STM32F72xxx STM32F73xxx	ES0360 Rev5 (Feb 2020)
	STM32L496xx STM32L4A6xx	ES0335 Rev18 (Feb 2024)
PWRC	STM32WB09xE	ES0584 Rev1 (Sep 2023)	Add section:  SMPS with BOM1 does not work properly at 4MHz Description With Bill Of Material  BOM1 (inductor=1.5µH and capacitor=2.2µF) , the SMPS can’t deliver the right output voltage when Frequency switching (Fs) is settled to 4MHz. Workaround Set the  Frequency switching (Fs) to 8MHz if BOM1 is needed (low profile height components). if no low profile is needed, use the standard BOM3 (inductor=10µH and capacitor=4.7µF).	Oct 2024
Document	STM32H523xx STM32H533xx	ES0621 Rev1 (Mar 2024)	Change bottom pages with the correct Errata sheet ID Current: ES0521. Expected: ES0621.	Sep 2024