on
2024-06-06
2:00 AM
- edited on
2025-07-10
6:34 AM
by
Laurids_PETERSE
This article includes preliminary updates of STM32 MCU errata sheets reported since 1st January 2024. It highlights the current description requiring update and the expected one if available.
The purpose of this article is to deliver any expected updates to our MCU errata sheets prior to actual documentation releases. We wish to be transparent with our updates and provide them as fast as possible, to assist you in your design process.
This article is updated on a quarterly basis. Once these preliminary updates are manifested in the errata sheets, this article is refreshed with new information.
Moving forward, we are also working on providing errata sheet releases on a more frequent basis.
IMPORTANT NOTICE - READ CAREFULLY:
Function | Series/Lines | Doc Reference - Revision | Description | Date of added update |
SPI |
STM32F427xx STM32F437xx STM32F429xx STM32F439xx |
(Feb 2025) |
Add section: Corrupted last bit of data and/or CRC, received in Master mode with delayed SCK feedback Description Workaround
|
Mar 2024
|
System |
STM32H742xI |
ES0392 Rev13 |
HASH input data may be corrupted when DMA is used Current: Description Workaround Expected: Description Workaround |
Jun 2025
|
STM32H745xx STM32H747xx STM32H755xx STM32H757xx |
(Sep 2024) |
|||
STM32G471xx |
(Jun 2024) |
Remove section: The same errata looks to appear 2 times : 2.2.5 MCU cannot enter in Standby mode when HSE bypass used |
Jun 2025 |
|
STM32U375xx STM32U385xx |
(Feb 2025) |
LSE crystal oscillator may be disturbed by transitions on PC13 Current: Description Expected: Description |
Jun 2025 |
|
IWDG |
STM32F100x4 STM32F100x6 |
(Jul 2022) |
Remove sections: Delete duplicated sections: - RVU flag not cleared at low APB clock frequency - PVU flag not cleared at low APB clock frequency |
Mar |
STM32F10xx4 STM32F10xx6 |
(Jun 2022) |
|||
STM32F101xF |
(Jul 2022) |
|||
STM32F101xC |
(Jun 2022) |
|||
STM32F105xx STM32F107xx |
(Jun 2022) |
|||
STM32F100xC STM32F100xD STM32F100xE |
(Aug 2022) |
|||
HRTIM |
STM32F334x4 |
(Aug 2021) |
Table 4. Summary of silicon limitations Current: A = limitation present, workaround available Expected: With N = limitation present, no workaround available |
Nov 2024 |
ADC |
STM32L412xx |
ES0456 Rev6 (Nov 2024) |
Remove section: Delete duplicated section: "2.6.9 Writing ADCx_JSQR when JADCSTART and JQDIS are set might lead to incorrect behavior" should be removed. It is duplicated with "2.6.1 Writing ADC_JSQR when JADCSTART and JQDIS are set may lead to incorrect behavior" |
Dec 2024 |
CEC |
STM32H7A3xI STM32H7A3xG |
ES0478 Rev11 (Apr 2022) |
Add section: Unexpected TXERR flag during a message transmission. Description During the transmission of a 0 or a 1, the HDMI-CEC drives the open-drain output to high-Z, so that the external pull-up implements a voltage rising ramp on the CEC line. |
Dec 2024 |
OCTOSPI |
STM32H7A3xI STM32H7A3xG |
ES0478 Rev11 (Apr 2022) |
Add section: Transactions are limited to 8 Mbytes in OctaRAM™ memories. Description When the controller is configured in Macronix OctaRAM™ mode, by setting the MTYP[2:0] bitfield of the OCTOSPI_DCR1 register to 011, only 13 bits of row address are decoded and sent to the memory, meaning that only 8 K of 1-Kbyte blocks can be accessed (8 Mbytes). |
Dec 2024 |
Summary of device errata |
STM32H7A3xI STM32H7A3xG STM32H7B0xB STM32H7B3xI |
(Apr 2022) |
Remove note: 1. This erratum is fixed in part numbers with RSS version 3.1.0 associated to bootloader revision 9.2. It is present in part |
Jun 2025 |
Applicability |
(Apr 2022) |
Table 1. Device summary Add: STM32H7A3LG in the part numbers list. |
Jun 2025 |