STM32 MCU errata sheets: Expected preliminary updates

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Introduction

This article includes preliminary updates of STM32 MCU errata sheets reported since 1st January 2024. It highlights the current description requiring update and the expected one if available.

The purpose of this article is to deliver any expected updates to our MCU errata sheets prior to actual documentation releases. We wish to be transparent with our updates and provide them as fast as possible, to assist you in your design process.
This article is updated on a quarterly basis. Once these preliminary updates are manifested in the errata sheets, this article is refreshed with new information.
Moving forward, we are also working on providing errata sheet releases on a more frequent basis.

IMPORTANT NOTICE - READ CAREFULLY:

• STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to this article at any time without notice.
• Information in this article supersedes and replaces information previously supplied in any prior versions of this article.

• The following table gives a quick reference to the preliminary documentation updates which may be changed or improved without notice.
• This article will be reviewed on a quarterly basis and applied updates will be removed from the table.
• The hyperlinks under "Doc Reference - Revision" provides a direct link to the specific document page where the description is located.

Summary of documentation updates: "STM32 MCU errata sheets"

Function	Series/Lines	Doc Reference - Revision	Description	Date of added update
SPI	STM32F427xx STM32F437xx STM32F429xx STM32F439xx	ES0206 Rev23 (Feb 2025)	Add section:  Corrupted last bit of data and/or CRC, received in Master mode with delayed SCK feedback Description When performing a receive transaction in I2S or SPI Master mode, the last bit of the transacted frame is not captured when the signal provided by an internal feedback loop from the SCK pin exceeds a critical delay. The lastly transacted bit of the stored data then keeps the value from the pattern received previously. As a consequence, the last receive data bit may be wrong, and/or the CRCERR flag can be unduly asserted in the SPI mode if any data under checksum, and/or just the CRC pattern is wrongly captured. In SPI mode, data are synchronous with the APB clock. A delay of up to two APB clock periods can thus be tolerated for the internal feedback delay. The I2S mode is more sensitive than the SPI mode, especially in the case where an odd I2S prescaler factor is set and the APB clock is the system clock divided by two. In this case, the internal feedback delay is lower than 1.5 APB clock period. The main factors contributing to the delay increase are low VDD level, high temperature, high SCK pin capacitive load, and low SCK I/O output speed. The SPI communication speed has no impact. Workaround The following workarounds can be adopted, jointly or individually: • Decrease the APB clock speed. • Configure the I/O pad of the SCK pin to be faster. The following table gives the maximum allowable APB frequency (that still prevents the issue from occurring) versus GPIOx_OSPEEDR output speed for the SCK pin, with a 30 pF capacitive load.	Mar 2024
System	STM32WBA5x	ES0592 Rev5 (Nov 2024)	Add section: Title: LSE low swing input clock signals not supported Description: The use of LSE in bypass mode with low swing signals is unreliable and must thus be proscribed. This does not impact crystal mode.  Workaround: None.	Dec 2024
	STM32WBA50 KG	ES0637 Rev1 (Sep 2024)
IWDG	STM32F100x4 STM32F100x6 STM32F100x8 STM32F100xB	ES093 Rev8 (Jul 2022)	Remove sections: Delete duplicated sections: - RVU flag not cleared at low APB clock frequency - PVU flag not cleared at low APB clock frequency	Mar 2024
	STM32F10xx4 STM32F10xx6	ES0348 Rev10 (Jun 2022)
	STM32F101xF STM32F101xG STM32F103xF STM32F103xG	ES0346 Rev7 (Jul 2022)
	STM32F101xC STM32F101xD STM32F101xE STM32F103xC STM32F103xD STM32F103xE	ES0340 Rev17 (Jun 2022)
	STM32F105xx STM32F107xx	ES022 Rev11 (Jun 2022)
	STM32F100xC STM32F100xD STM32F100xE	ES0136 Rev7 (Aug 2022)
HRTIM	STM32F334x4 STM32F334x6 STM32F334x8	ES0258 Rev8 (Aug 2021)	Table 4. Summary of silicon limitations Current: A = limitation present, workaround available Expected: With N = limitation present, no workaround available	Nov 2024
ADC	STM32L412xx STM32L422xB	ES0456 Rev6 (Nov 2024)	Remove section: Delete duplicated section: "2.6.9 Writing ADCx_JSQR when JADCSTART and JQDIS are set might lead to incorrect behavior" should be removed. It is duplicated with "2.6.1 Writing ADC_JSQR when JADCSTART and JQDIS are set may lead to incorrect behavior"	Dec 2024
CEC	STM32H7A3xI STM32H7A3xG STM32H7B0xB STM32H7B3xI	ES0478 Rev11 (Apr 2022)	Add section: Unexpected TXERR flag during a message transmission. Description  During the transmission of a 0 or a 1, the HDMI-CEC drives the open-drain output to high-Z, so that the external pull-up implements a voltage rising ramp on the CEC line. In some load conditions, with several powered-off devices connected to the HDMI-CEC line, the rising voltage may not drive the HDMI-CEC GPIO input buffer to VIH within two HDMI-CEC clock cycles from the high-Z activation to TXERR flag assertion. Workaround Limit the maximum number of devices connected to the HDMI-CEC line to ensure the GPIO VIH threshold is reached within a time of two HDMI-CEC clock cycles (~61 µs). The maximum equivalent 10%-90% rise time for the HDMI-CEC line is 111.5 µs, considering a VIH threshold equal to 0.7 x VDD.	Dec 2024
OCTOSPI	STM32H7A3xI STM32H7A3xG STM32H7B0xB STM32H7B3xI	ES0478 Rev11 (Apr 2022)	Add section: Transactions are limited to 8 Mbytes in OctaRAM™ memories. Description  When the controller is configured in Macronix OctaRAM™ mode, by setting the MTYP[2:0] bitfield of the OCTOSPI_DCR1 register to 011, only 13 bits of row address are decoded and sent to the memory, meaning that only 8 K of 1-Kbyte blocks can be accessed (8 Mbytes). Workaround None. This limitation is not present for PSRAMs or HyperRAM™ memories.	Dec 2024
	STM32U59xxx STM32U5Axxx	ES0553 Rev4 (Apr 2024)	Add section: Octospi external memory read issue after exiting Stop 2 or Stop 3 mode, when using DQS and Delay block. Description  After exiting Stop 2 or Stop 3 mode, the first read in Octospi external memory can return erroneous data when the both conditions are met: OCTOSPI DQS is enabled and Delay block is enabled. Workaround After exiting Stop 2 or Stop 3 mode, make a dummy read in external memory before reading the external memory.	Mar 2025
AES	STM32U59xxx STM32U5Axxx	ES0553 Rev4 (Apr 2024)	Add section: AES suspend registers name is changed Description  In some reference manuals, the AES suspend registers section does not have the correct name. It should read AES_SUSPRx instead of AES_SUSPxR. Workaround No application workaround is required or applicable.	Mar 2025
DSI	STM32U59xxx STM32U5Axxx	ES0553 Rev4 (Apr 2024)	Add section: Title: EoT sync error can be reported by some displays Description: The differential line stay at logic 0 state for 2 byte time at the end of a HS packet transmission and before switching to LP state. It doesn’t impact the physical layer as it is seen as 2 extra bytes. It shall not impact the protocol layer as packets are not corrupted, but some display may signal an EoT sync error without altering the displayed image or functionality.  Workaround: Do not consider EoT sync error response from a display	Mar 2025
			Add section: Title: DSI PHY false contention detection in HS Description: The DSI PHY’s contention detector reports false contentions in HS.  Workaround:  Do not use contention detection in high-speed (HS) circuits (PE3/PE4 flags).	Mar 2025