STM32 MCU errata sheets: Expected preliminary updates

STM32G471xx
STM32G473xx
STM32G474xx
STM32G483xx
STM32G484xx

ES0430 Rev9

(Jun 2024)

Remove section:

The same errata looks to appear 2 times :

2.2.5 MCU cannot enter in Standby mode when HSE bypass used
2.2.10 Device cannot enter Standby mode when HSE bypass used as system clock

Jun 2025

Add section: 

Description:

When HASH transfers data using a channel from DMA1 or DMA2, utilizing another channel from these DMAs to manage other peripherals can cause HASH input data corruption.

Workaround

Apply one of the following measures:

• During a HASH data transfer using DMA1, make sure that no DMA channels are enabled on DMA2 (and vice versa).

Additionally, set bit 20 in the DMA_SxCR register, where 'x' is the channel used for HASH data transfer.

• Use the interrupt or polling mode to transfer data to the HASH peripheral when DMA1 or DMA2 channels cannot be disabled during the HASH transfer.

ES0620 Rev5

Aug 2026

Add section:

TCM ECC Initialization Required Before First Use

Description

Chapter SRAM and its ECC subsection describe the ECC behavior for SRAM memories. However, it is not explicitly stated that the TCM memories (ITCM/DTCM) also implement ECC protection and require an initialization phase before their first use.

The ECC management of the TCM is performed by the Arm Cortex-M55 CPU. When a TCM location has not been initialized, its ECC bits contain undefined values. A read access performed before the first write to the corresponding location may therefore generate an ECC error.

As described in the Arm Cortex-M55 Processor Technical Reference Manual (r0p2), ECC memory protection behavior and error detection/processing, all ECC-protected TCM locations must be initialized before being accessed by load instructions.

Impact
--------

If DTCM memory is accessed before initialization:
-ECC errors may be detected by the Cortex-M55.
-A Precise ECC Error (PECC) may be generated.
-The application may enter the HardFault handler.
-Read operations (LDR instructions) performed on uninitialized TCM locations may fail.

Conditions
--------------
The issue occurs when:
-DTCM or ITCM ECC protection is active.
-The startup code does not initialize the entire TCM region before the first read access.
-Software performs a read operation on locations that have never been written since reset.

Workaround
-----------------
- Initialize the complete TCM memory region before its first use.
For example, the DTCM Baseline region located at address range: 0x30000000 - 0x3001FFFF
can be cleared during startup by adding the following code in the Reset_Handler, immediately after the stack pointer initialization and before calling SystemInit().

Example workaround startup code
------------------------
Reset_Handler:
    ldr r0, =_sstack
    msr MSPLIM, r0
    ldr r0, =_estack
    mov sp, r0              /* set stack pointer */

    /***************** Code to be added - start ***********************/
    /* Clear D-TCM */
    ldr R0, =0x30000000
    ldr R1, =0x30020000
    mov R2, #0
    clear_dtcm:
    str R2, [R0]
    add R0, R0, #4
    cmp R0, R1
    bcc clear_dtcm
    /***************** Code to be added - end *************************/

    /* Call the clock system initialization function. */
    bl SystemInit

STM32F100x4 STM32F100x6
STM32F100x8 STM32F100xB

ES093 Rev8

(Jul 2022)

Remove sections:

Delete duplicated sections:

- RVU flag not cleared at low APB clock frequency

- PVU flag not cleared at low APB clock frequency

Mar
2024

STM32F10xx4 STM32F10xx6

ES0348 Rev10

(Jun 2022)

STM32F101xF
STM32F101xG STM32F103xF
STM32F103xG 

ES0346 Rev7

(Jul 2022)

STM32F101xC
STM32F101xD
STM32F101xE
STM32F103xC
STM32F103xD
STM32F103xE

ES0340 Rev17

(Jun 2022)

STM32F105xx STM32F107xx

ES022 Rev11

(Jun 2022)

ES0136 Rev7

(Aug 2022)

STM32F334x4
STM32F334x6
STM32F334x8

ES0258 Rev8

(Aug 2021)

Table 4. Summary of silicon limitations

Current:

A = limitation present, workaround available

Expected:

With N = limitation present, no workaround available

Nov 2024

STM32L412xx
STM32L422xB

ES0456 Rev6 (Nov 2024)

Remove section:

Delete duplicated section:

"2.6.9 Writing ADCx_JSQR when JADCSTART and JQDIS are set might lead to incorrect behavior" should be removed. It is duplicated with "2.6.1 Writing ADC_JSQR when JADCSTART and JQDIS are set may lead to incorrect behavior"

ES0523 Rev6

Update section: 2.5.11 An ADC instance may impact the accuracy of another ADC instance at specific conditions

Expected:

STM32G431xx

ES0431 Rev9

ES0430 Rev9

Update section: 2.7.11 An ADC instance may impact the accuracy of another ADC instance at specific conditions

Expected:

STM32H7A3xI STM32H7A3xG
STM32H7B0xB STM32H7B3xI

ES0478 Rev11 (Apr 2022)

Add section:

Unexpected TXERR flag during a message transmission.

Description 

During the transmission of a 0 or a 1, the HDMI-CEC drives the open-drain output to high-Z, so that the external pull-up implements a voltage rising ramp on the CEC line.
In some load conditions, with several powered-off devices connected to the HDMI-CEC line, the rising voltage may not drive the HDMI-CEC GPIO input buffer to VIH within two HDMI-CEC clock cycles from the high-Z activation to TXERR flag assertion.
Workaround
Limit the maximum number of devices connected to the HDMI-CEC line to ensure the GPIO VIH threshold is reached within a time of two HDMI-CEC clock cycles (~61 µs).
The maximum equivalent 10%-90% rise time for the HDMI CEC line is 111.5 µs, considering a VIH threshold equal to 0.7 x VDD.

STM32H7A3xI STM32H7A3xG
STM32H7B0xB STM32H7B3xI

ES0478 Rev11 (Apr 2022)

Add section:

Transactions are limited to 8 Mbytes in OctaRAM™ memories.

Description 

When the controller is configured in Macronix OctaRAM™ mode, by setting the MTYP[2:0] bitfield of the OCTOSPI_DCR1 register to 011, only 13 bits of row address are decoded and sent to the memory, meaning that only 8 K of 1-Kbyte blocks can be accessed (8 Mbytes).
Workaround
None.
This limitation is not present for PSRAMs or HyperRAM™ memories.

STM32H7A3xI STM32H7A3xG STM32H7B0xB STM32H7B3xI

ES0478 Rev11

(Apr 2022)

Table 1. Device summary

Add:

STM32H7A3LG in the part numbers list.

ES022 Rev11

Remove section:

Delete duplicated sections

- PWM re-enabled in automatic output enable mode despite of system break

- TRGO and TRGO2 trigger output failure

- Consecutive compare event missed in specific conditions

- Output compare clear not working with external counter reset

ES0348 Rev10

(Jun 2022)

ES0263 Rev4

Add in Table 2. Summary of device limitations:

Add note in table 3 for 2.2.3 Secure firmware install (SFI):

1. This erratum is fixed in part numbers with RSS version 3.1.0 associated to bootloader revision 9.3. It is present in part
numbers with RSS version 2.5.1 associated to bootloader revision 9.2 and with RSS version 2.5.0 associated to bootloader revision 9.1. 
The bootloader revision can be read at address 0x1FF1 E7FE: the value 0x93 corresponds to revision 9.3. The RSS version can be read by calling RSS_getVersion().

ES0506 Rev5

Add in Table 2. Summary of device limitations:

Add section: 

Some reference manual revisions may wrongly mentioned the PCx MODE and value while it is reserved.