STM32 MCU reference manuals: Expected preliminary updates

KDJEM.1 · ‎2024-06-10

Introduction

This article includes preliminary updates of STM32 MCU reference manuals reported since 1st January 2024. It highlights the current description requiring update and the expected one if available.

The purpose of this article is to deliver any expected updates to our MCU reference manuals prior to actual documentation releases. We wish to be transparent with our updates and provide them as fast as possible, to assist you in your design process.
This article is updated on a monthly basis. Once these preliminary updates are manifested in the reference manuals, this article is refreshed with new information.
Moving forward, we are also working on providing reference manual releases on a more frequent basis.

IMPORTANT NOTICE - READ CAREFULLY:

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to this article at any time without notice.
Information in this article supersedes and replaces information previously supplied in any prior versions of this article.

The following table gives a quick reference to the preliminary documentation updates which may be changed or improved without notice.
This article will be reviewed on a monthly basis and applied updates will be removed from the table.
The hyperlinks under "Doc Reference - Revision" provides a direct link to the specific document page where the description is located.

Summary of documentation updates : "STM32 MCU reference manuals"

Function	Series(Lines) / Doc Reference Revision	Update Location	Current Description / Expected Description	Date of added update
NVIC	STM32L41xxx STM32L42xxx STM32L43xxx STM32L44xxx STM32L45xxx STM32L46xxx RM0394 Rev4 (Oct 2018)	Table 46. STM32L41xxx /42xxx/43xxx /44xxx/45xxx /46xxx vector table	Current: Address of RCC and EXTI0 Acronyms is 0x0000 005C Expected: Addresses of RCC and EXTI0 Acronyms are 0x0000 0054 and 0x0000 0058 respectively	Mar 2024
			Current: "SPI2⁽⁴⁾" with note "4. Not available on STM32L432xx and STM32L442xx devices." Expected: Remove note (4) for SPI2	Mar 2024
			Current: "TIM6 global and DAC1⁽¹⁾ underrun interrupts" with note "1. Not available on STM32L41xxx and STM32L42xxx devices." Expected: "TIM6 global and DAC2⁽⁵⁾ underrun interrupts" with note"5. Available on STM32L43xxx and STM32L44xxx devices only."	Mar 2024
	STM32H523xx STM32H533xx STM32H562xx STM32H563xx STM32H573xx RM0481 Rev2 (Apr 2024)	Table 144. STM32H562/ 563/573xx vector table	Current: wrong address mapping Expected:	Aug 2024
		Table 145. STM32H523/ 533xx vector table	Current: wrong address mapping Expected:	Aug 2024
RCC	STM32H742 STM32H743 STM32H753 STM32H750 RM0433 Rev8 (Jan 2023)	Table 60. Kernel clock distribution overview	Current: Maximum allowed frequency [MHz] for ADC1,2,3 are: VOS0 100⁽⁴⁾ VOS1 100⁽⁴⁾ VOS2 80⁽⁴⁾ VOS3 80⁽⁴⁾ with note "4. With a duty cycle close to 50%, meaning that DIV[P/Q/R]x values shall be even. For SDMMCx, the duty cycle shall be 50% when supporting DDR." Expected: Maximum allowed frequency [MHz] for ADC1,2,3 are: VOS0 80 VOS1 80 VOS2 40 VOS3 40	Mar 2024
	STM32F72xxx STM32F73xxx RM0431 Rev3 (Jun 2018)	5.3.13 RCC APB1 peripheral clock enable register (RCC_ APB1ENR)	Current: "Bit 11 WWDGEN: Window watchdog clock enable This bit is set and cleared by software." Expected: "Bit 11 WWDGEN: Window watchdog clock enable This bit is set by software to enable the window watchdog clock. It is reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset."	Jun 2024
	STM32F75xxx STM32F74xxx RM0385 Rev8 (Mar 2018)			Jun 2024
	STM32F413 STM32F423 RM0430 Rev8 (May 2018)	6.1.1 System reset	Current: "A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain." Expected: "A system reset sets all registers to their reset values unless specified otherwise in the register description."	Jul 2024
	STM32WBA5 RM0493 Rev4 (Jun 2024)	Figure 34. Clock tree	Current: Expected:	Jul 2024
FLASH	STM32G4 RM0440 Rev8 (Feb 2024)	Table 28. Flash module - 64/128Kbytes organization (64 bits read width)	Current: Expected:	Mar 2024
	STM32F75xxx STM32F74xxx RM0385 Rev8 (Mar 2018)	3.3.7 Flash programming sequences	Current: "If this cannot be done safely, it is recommended to flush and/or desactivate the ART accelerator by setting respectively the bits ARTRST or ARTEN of the FLASH_CR register" Expected: "If this cannot be done safely, it is recommended to flush and/or desactivate the ART accelerator by setting respectively the bits ARTRST or ARTEN of the FLASH_ACR register"	Jun 2024
	STM32F72xxx STM32F73xxx RM0431 Rev3 (Jun 2018)	3.3.7 Flash programming sequences		Jun 2024
	STM32F75xxx STM32F74xxx RM0385 Rev8 (Mar 2018)	3.3.6 Flash erase sequences	Current: "2. Set the SER bit and select the sector out of the 8 in the main memory block) wished to erase (SNB) in the FLASH_CR register" Expected: "2. Set the SER bit and select the sector number of the user memory block you wish to erase (SNB) in the FLASH_CR register"	Jun 2024
	STM32F72xxx STM32F73xxx RM0431 Rev3 (Jun 2018)	3.3.6 Flash erase sequences		Jun 2024
	STM32F72xxx STM32F73xxx RM0431 Rev3 (Jun 2018)	Table 11. OTP area organization	Current: - "OPT14" - "OPT15" Expected: - "OTP14" - "OTP15"	Jun 2024
	STM32F72xxx STM32F73xxx RM0431 Rev3 (Jun 2018)	Table 3. STM32F72xxx and STM32F732xx /F733xx Flash memory organization	Current: "Block base address on ICTM interface" Expected: "Block base address on ITCM interface"	Jun 2024
	STM32F72xxx STM32F73xxx RM0431 Rev3 (Jun 2018)	Table 4. STM32F730xx Flash memory organization		Jun 2024
	STM32F413 STM32F423 RM0430 Rev8 (May 2018)	3.6.3 Read protection (RDP)	Current: "Note: The JTAG port is permanently disabled when Level 2 is active (acting as a JTAG fuse). As a consequence, boundary scan cannot be performed. STMicroelectronics is not able to perform analysis on defective parts on which the Level 2 protection has been set." Expected: "Note: The JTAG port is permanently disabled when Level 2 is active (acting as a JTAG fuse). As a consequence, boundary scan cannot be performed. STMicroelectronics is not able to perform analysis on defective parts on which the Level 2 protection has been set. Note: If the read protection is set while the debugger is still connected through JTAG/SWD, apply a POR (power-on reset)."	Jul 2024
	STM32F413 STM32F423 RM0430 Rev8 (May 2018)	3.8.6 Flash option control register (FLASH_ OPTCR)	Current: "Reset value: 0x0FFF FFED." Expected: "Reset value: 0x7FFF AAED."	Aug 2024
	STM32H745 STM32H755 STM32H747 STM32H757 RM0399 Rev4 (Jun 2023) STM32H7A3 STM32H7B3 STM32H7B0 RM0455 Rev11 (Dec 2023) STM32H742 STM32H743 STM32H753 STM32H750 RM0433 Rev8 (Jan 2023) STM32H723 STM32H733 STM32H725 STM32H735 STM32H730 RM0468 Rev3 (Dec 2021) STM32H7Rx/ 7Sx RM0477 Rev7 (Jul 2024)	FLASH erase operations	Current: "1. Check and clear (optional) all the error flags due to previous programming/erase operation. Refer to Section 5.7: FLASH error management for details." Expected: "Remove "optional" word."	Aug 2024
		Table xx. Flash interrupt request	Expected: Add notes to Clear flag to resume operation for: -Write protection error: Check this flag after an erase operation. -Programming sequence error and Inconsistency error: Check and clear all the (PGSEER, INCERR, STRBERR) error flags due to previous write operation.	Aug 2024
ADC	STM32F413 STM32F423 RM0430 Rev8 (May 2018)	13.9 Temperature sensor	Current: "The temperature sensor can be used to measure the ambient temperature (TA) of the device." Expected: "The temperature sensor can be used to measure the junction temperature (TJ) of the device."	Jun 2024
HRTIM	STM32G4 RM0440 Rev8 (Feb 2024)	Figure 241. Burst mode emulation example	Current: Expected:	Mar 2024
TIM	STM32G4 RM0440 Rev8 (Feb 2024)	Figure 352. Measuring time interval between edges on three signals	Current: Expected: Invert XOR signal	Mar 2024
USART /UART	STM32G4 RM0440 Rev8 (Feb 2024)	37.5.7 USART baud rate generation	Current: Wrong parameter name: "usart_ker_ckpres" Expected: Replace "usart_ker_ckpres" per "usart_ker_ck_pres"	Mar 2024
LPUART	STM32L0x3 RM0367 Rev8 (Feb 2022)	Table 150. Error calculation for programmed baud rates at fck = 32 MHz	Current: Table 150. Error calculation for programmed baud rates at fck = 32 MHz Expected: Table 150. Error calculation for programmed baud rates at fck = 32.768 KHz	May 2024
RTC	STM32H523xx STM32H533xx STM32H562xx STM32H563xx STM32H573xx RM0481 Rev2 (Apr 2024)	Table 495. PI8 configuration	Current: "Table 495. PI8 configuration" Expected: "Table 495. PI8/PB2 configuration"	Jun 2024
Device electronic signature	STM32G4 RM0440 Rev8 (Feb 2024)	48.3 Package data register	Current: 00010: LQFP100 (all devices) and LQFP80 (for category 2 and category 3 devices) 00101: WLCSP81 Expected: 00010: LQFP100 (all devices) and LQFP80 (for category 2 devices) 00101: WLCSP81 and LQFP80 (for category 3 devices)	Mar 2024
ETH	STM32H723 STM32H733 STM32H725 STM32H735 STM32H730 RM0468 Rev3 (Dec 2021)	Table 543. Ethernet peripheral pins	Current: "ETH_PHY_INTN" Expected: Remove "ETH_PHY_INTN" from Table Ethernet peripheral pins	Apr 2024
ETH	STM32H742 STM32H743 STM32H753 STM32H750 RM0433 Rev8 (Jan 2023)	Table 522. Ethernet peripheral pins	Current: "ETH_PHY_INTN" Expected: Remove "ETH_PHY_INTN" from Table Ethernet peripheral pins	May 2024
PWR	STM32U0 RM0503 Rev2 (Mar 2024)	4.4.2 Power control register 2 (PWR_CR2)	Current: Bit 10 USV⁽¹⁾ Bit 4 PVME1⁽¹⁾ with note "1. Available on STM32U0 devices only." Expected: Bit 10 USV⁽¹⁾ Bit 4 PVME1⁽¹⁾ with note "1. Available on STM32U0x3xx devices only."	Apr 2024
	STM32F75xxx STM32F74xxx RM0385 Rev8 (Mar 2018)	4.1.3 Battery backup domain	Current: If no external battery is used in the application, it is recommended to connect the VBAT pin to VDD with a 100 nF external decoupling ceramic capacitor in parallel. Expected: If no external battery is used in the application, it is recommended to connect VBAT externally to VDD through a 100 nF external ceramic capacitor	Jun 2024
	STM32F72xxx STM32F73xxx RM0431 Rev3 (Jun 2018)	4.1.3 Battery backup domain		Jun 2024
	STM32F413 STM32F423 RM0430 Rev8 (May 2018)	5.2.3 Programmable voltage detector (PVD)	Current: A PVDO flag is available, in the PWR power control/status register (PWR_CSR), to indicate if VDD is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated when VDD drops below the PVD threshold and/or when VDD rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration. As an example the service routine could perform emergency shutdown tasks. Expected: A PVDO flag is available, in the PWR power control/status register (PWR_CSR), to indicate if VDD is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The rising/falling edge sensitivity of the EXTI Line16 should be configured according to PVD output behavior i.e. if the EXTI line 16 is configured to rising edge sensitivity, the interrupt will be generated when VDD drops below the PVD threshold. As an example the service routine could perform emergency shutdown tasks.	Jul 2024
	STM32U0 RM0503 Rev2 (Mar 2024)	4.4.2 Power control register 2 (PWR_CR2)	Current: "1. Available on STM32U0x3xx devices only." Expected: Remove note "1. Available on STM32U0x3xx devices only."	Jul 2024
	STM32F76xxx STM32F77xxx RM0410 Rev5 (Jul 2024)	4.3 Low-power modes	Current: "The MCU exits from Standby low-power mode through an external reset (NRST pin), an IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event occurs" Expected: "The MCU exits from Standby low-power mode through an external reset (NRST pin), an IWDG reset, a rising or falling on one of the enabled WKUPx pins or a RTC event occurs"	Aug 2024
	STM32F75xxx STM32F74xxx RM0385 Rev8 (Jun 2018)
	STM32F72xxx STM32F73xxx RM0431 Rev3 (Jun 2018)
COMP	STM32F303xB STM32F303xC STM32F303xD STM32F303xE STM32F303x6 STM32F303x8 STM32F328x8 STM32F358xC STM32F398xE RM0316 Rev10 (Jan 2024)	17.5.3 COMP3 control and status register (COMP3_CSR)	Current: Bits 3:2 COMP3MODE[1:0]: Comparator 3 mode (only in STM32F303xB/C and STM32F358xC devices.) These bits control the operating mode of the comparator 3 and allows to adjust the speed/consumption. 00: Ultra-low power 01: Low-power 10: Medium speed 11: High speed Expected: Bits 3:2 COMP3MODE[1:0]: Comparator 3 mode (only in STM32F303xB/C and STM32F358xC devices.) These bits control the operating mode of the comparator 3 and allows to adjust the speed/consumption. 00: High speed 01: Medium speed 10: Low-power 11: Ultra-low-power	Apr 2024
	STM32F303xB STM32F303xC STM32F303xD STM32F303xE STM32F303x6 STM32F303x8 STM32F328x8 STM32F358xC STM32F398xE RM0316 Rev10 (Jan 2024)	17.5.4 COMP4 control and status register (COMP4_CSR)	Current: Bits 3:2 COMP4MODE[1:0]: Comparator 1 mode (only in STM32F303xB/C and STM32F358xC devices) These bits control the operating mode of the comparator 4 and allows to adjust the speed/consumption. 00: Ultra-low-power 01: Low-power 10: Medium speed 11: High speed Expected: Bits 3:2 COMP4MODE[1:0]: Comparator 1 mode (only in STM32F303xB/C and STM32F358xC devices) These bits control the operating mode of the comparator 4 and allows to adjust the speed/consumption. 00: High speed 01: Medium speed 10: Low-power 11: Ultra-low-power	Apr 2024
	STM32F303xB STM32F303xC STM32F303xD STM32F303xE STM32F303x6 STM32F303x8 STM32F328x8 STM32F358xC STM32F398xE RM0316 Rev10 (Jan 2024)	17.5.5 COMP5 control and status register (COMP5_CSR)	Current: Bits 3:2 COMP5MODE[1:0]: Comparator 5 mode (Only in STM32F303xB/C and STM32F358xC devices) These bits control the operating mode of the comparator 5 and allows to adjust the speed/consumption. 00: Ultra-low power 01: Low-power 10: Medium speed 11: High speed Expected: Bits 3:2 COMP5MODE[1:0]: Comparator 5 mode (Only in STM32F303xB/C and STM32F358xC devices) These bits control the operating mode of the comparator 5 and allows to adjust the speed/consumption. 00: High speed 01: Medium speed 10: Low-power 11: Ultra-low-power	Apr 2024
	STM32F303xB STM32F303xC STM32F303xD STM32F303xE STM32F303x6 STM32F303x8 STM32F328x8 STM32F358xC STM32F398xE RM0316 Rev10 (Jan 2024)	17.5.6 COMP6 control and status register (COMP6_CSR)	Current: Bits 3:2 COMP6MODE[1:0]: Comparator 6 mode (Only in STM32F303xB/C and STM32F358xC devices) These bits control the operating mode of the comparator 6 and allows to adjust the speed/consumption. 00: Ultra-low power 01: Low-power 10: Medium speed 11: High speed Expected: Bits 3:2 COMP6MODE[1:0]: Comparator 6 mode (Only in STM32F303xB/C and STM32F358xC devices) These bits control the operating mode of the comparator 6 and allows to adjust the speed/consumption. 00: High speed 01: Medium speed 10: Low-power 11: Ultra-low-power	Apr 2024
	STM32F303xB STM32F303xC STM32F303xD STM32F303xE STM32F303x6 STM32F303x8 STM32F328x8 STM32F358xC STM32F398xE RM0316 Rev10 (Jan 2024)	17.5.7 COMP7 control and status register (COMP7_CSR)	Current: Bits 3:2 COMP7MODE[1:0]: Comparator 7 mode (Only in STM32F303xB/C and STM32F358xC devices) These bits control the operating mode of the comparator 7 and allows to adjust the speed/consumption. 00: Ultra-low power 01: Low-power 10: Medium speed 11: High speed Expected: Bits 3:2 COMP7MODE[1:0]: Comparator 7 mode (Only in STM32F303xB/C and STM32F358xC devices) These bits control the operating mode of the comparator 7 and allows to adjust the speed/consumption. 00: High speed 01: Medium speed 10: Low-power 11: Ultra-low-power	Apr 2024
Documen-tation conven-tions	STM32G4 RM0440 Rev8 (Feb 2024)	Table 1. STM32G4 series memory density	Current: Expected:	Mar 2024
DBG	STM32F413 STM32F423 RM0430 Rev8 (May 2018)	34.16.4 Debug MCU APB1 freeze register (DBGMCU_ APB1_FZ)	Current: Missing "DBG_LPTIM1_STOP" bit description in "DBGMCU_APB1_FZ" register Expected: Add Bit 9 DBG_LPTIM1_STOP: LPTMI1 counter stopped when core is halted 0: The clock of LPTIM1 counter is fed even if the core is halted 1: The clock of LPTIM1 counter is stopped when the core is halted	Jun 2024
Memory and bus architec-ture	STM32H745 STM32H755 STM32H747 STM32H757 RM0399 Rev4 (Jun 2023) STM32H7A3 STM32H7B3 STM32H7B0 RM0455 Rev11 (Dec 2023) STM32H742 STM32H743 STM32H753 STM32H750 RM0433 Rev8 (Jan 2023) STM32H723 STM32H733 STM32H725 STM32H735 STM32H730 RM0468 Rev3 (Dec 2021)	AXI interconnect - INI x AHB functionality modification register (AXI_INIx_FN_ MOD_AHB) section	Current: Bit 1 WR_INC_OVERRIDE: Converts all AHB-Lite read transactions to a series of single beat AXI transactions. 0: Override disabled 1: Override enabled Bit 0 RD_INC_OVERRIDE: Converts all AHB-Lite write transactions to a series of single beat AXI transactions, and each AHB-Lite write beat is acknowledged with the AXI buffered write response. 0: Override disabled 1: Override enabled Expected: Bit 1 WR_INC_OVERRIDE: Converts all AHB-Lite write transactions to a series of single beat AXI transactions, and each AHB-Lite write beat is acknowledged with the AXI buffered write response. 0: Override disabled 1: Override enabled Bit 0 RD_INC_OVERRIDE: Converts all AHB-Lite read transactions to a series of single beat AXI transactions. 0: Override disabled 1: Override enabled	Jul 2024
EXTI	STM32F75xxx STM32F74xxx RM0385 Rev8 (Mar 2018)	11.9.6 Pending register (EXTI_PR)	Current: "Reset value: undefined" Expected: "Reset value: 0x0000 0000"	Jun 2024
EXTI	STM32F72xxx STM32F73xxx RM0431 Rev3 (Jun 2018)	10.9.6 Pending register (EXTI_PR)		Jun 2024
Document Structure	STM32F72xxx STM32F73xxx RM0431 Rev3 (Jun 2018)	-	Current: In the PDF document: the bookmarks from 1 to 29 are duplicated. Expected: Delete duplicated bookmarks.	Apr 2024