Introduction
This article includes preliminary updates of STM32 MCU reference manuals reported since 1st January 2024. It highlights the current description requiring update and the expected one if available.
The purpose of this article is to deliver any expected updates to our MCU reference manuals prior to actual documentation releases. We wish to be transparent with our updates and provide them as fast as possible, to assist you in your design process.
This article is updated on a monthly basis. Once these preliminary updates are manifested in the reference manuals, this article is refreshed with new information.
Moving forward, we are also working on providing reference manual releases on a more frequent basis.
IMPORTANT NOTICE - READ CAREFULLY:
- STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to this article at any time without notice.
- Information in this article supersedes and replaces information previously supplied in any prior versions of this article.
- The following table gives a quick reference to the preliminary documentation updates which may be changed or improved without notice.
- This article will be reviewed on a monthly basis and applied updates will be removed from the table.
- The hyperlinks under "Doc Reference - Revision" provides a direct link to the specific document page where the description is located.
Summary of documentation updates : "STM32 MCU reference manuals"
| Function | Series(Lines) / Doc Reference Revision |
Update Location | Current Description / Expected Description |
Date of added update |
| NVIC |
STM32L41xxx STM32L42xxx STM32L43xxx STM32L44xxx STM32L45xxx STM32L46xxx
(Oct 2018) |
Table 46. STM32L41xxx |
Current: Address of RCC and EXTI0 Acronyms is 0x0000 005C Expected: Addresses of RCC and EXTI0 Acronyms are 0x0000 0054 and 0x0000 0058 respectively |
Mar 2024 |
|
Current: "SPI2(4)" with note "4. Not available on STM32L432xx and STM32L442xx devices." Expected: Remove note (4) for SPI2 |
Mar 2024 |
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|
Current: "TIM6 global and DAC1(1) underrun interrupts" with note "1. Not available on STM32L41xxx and STM32L42xxx devices." Expected: "TIM6 global and DAC2(5) underrun interrupts" with note"5. Available on STM32L43xxx and STM32L44xxx devices only." |
Mar 2024 |
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|
STM32H523xx
(Apr 2024) |
Table 144. STM32H562/ 563/573xx vector table
|
Current: wrong address mapping    Expected:    |
Aug 2024
|
|
|
Table 145. STM32H523/ 533xx vector table
|
Current: wrong address mapping   
Expected:    |
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| RCC |
STM32H742 STM32H743 STM32H753 STM32H750
(Jan 2023) |
Table 60. Kernel clock distribution overview |
Current: Maximum allowed frequency [MHz] for ADC1,2,3 are: with note "4. With a duty cycle close to 50%, meaning that DIV[P/Q/R]x values shall be even. For SDMMCx, the duty cycle shall be 50% when supporting DDR." Expected: Maximum allowed frequency [MHz] for ADC1,2,3 are: |
Mar 2024 |
|
STM32F72xxx STM32F73xxx
(Jun 2018) |
5.3.13 RCC APB1 peripheral clock enable register (RCC_ |
Current: "Bit 11 WWDGEN: Window watchdog clock enable Expected: "Bit 11 WWDGEN: Window watchdog clock enable |
Jun 2024 |
|
|
STM32F75xxx STM32F74xxx
(Mar 2018) |
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|
STM32F413
(May 2018) |
6.1.1 System reset |
Current: "A system reset sets all registers to their reset values except the reset flags in the clock Expected: "A system reset sets all registers to their reset values unless specified otherwise in the |
Jul 2024 |
|
|
STM32L41xxx
(Oct 2018)
|
Figure 13. Clock tree |
Current: 
Expected:  |
Sep 2024 |
|
|
STM32L41xxx
(Oct 2018) |
6.2.5 PLL |
Add: PLLP may sometimes be referred to as PLLSAI, as it's primary goal is to be source of audio clock. PLLQ may sometimes be referred to as PLL48M, because it's primary goal is to be source of 48MHz clock. |
Sep 2024 |
|
|
STM32L41xxx
(Oct 2018) |
6.4.27 Peripherals independent clock configuration register (RCC_CCIPR) |
Current: Note: When there is no PLL enabled, the HSI16 clock source is connected automatically to Expected: Note: When there is no PLL enabled, the HSI16 clock source is connected automatically to |
Sep 2024 |
|
|
STM32H503
(Mar 2023) |
10.4.6 LSE clock |
Current: This external clock is provided to the OSC32_IN pin while the OSC32_OUT pin must be left Expected: This external clock is provided to the OSC32_IN pin while the OSC32_OUT pin can be used as a GPIO |
Sep 2024 |
|
|
STM32H503
(Mar 2023) |
10.4.10 Clock security system (CSS) |
Current: In addition, the glitches on LSE can be filtered by setting LSEGFON. LSEGFON must be written when the LSE is disabled (LSEON = 0 and LSERDY = 0). Expected: Remove "In addition, the glitches on LSE can be filtered by setting LSEGFON. LSEGFON |
Sep 2024 |
|
|
STM32H523xx STM32H533xx STM32H562xx
RM0481 Rev2 |
11.8.44 RCC kernel clock configuration register (RCC_CCIPR5) |
Current: Bit 3 DACSEL: DAC sample and hold clock Expected: Bit 3 DACSEL: DAC sample and hold clock source selection |
Sep 2024 | |
|
STM32H523xx STM32H533xx STM32H562xx
RM0481 Rev2 |
11.8.8 RCC PLL clock source selection register (RCC_ PLL2CFGR) |
Current: 0: wide VCO range 192 to 836 MHz (default after reset) Expected: 0: wide VCO range 128 to 560MHz (default after reset) |
Sep 2024 | |
|
STM32H523xx STM32H533xx STM32H562xx
RM0481 Rev2 |
11.8.13 RCC PLL2 fractional divider register (RCC_ PLL2FRACR) |
Current: * PLL2FRACN can be between 0 and 213- 1 Expected: * FRACN2 can be between 0 and (2^13)-1 |
Sep 2024 | |
| FLASH |
STM32G4
(Feb 2024) |
Table 28. |
Current: 
Expected: |
Mar 2024 |
|
STM32F75xxx STM32F74xxx
(Mar 2018) |
3.3.7 Flash programming sequences |
Current: "If this cannot be done safely, it is recommended to flush and/or desactivate the Expected: "If this cannot be done safely, it is recommended to flush and/or desactivate the |
Jun 2024 |
|
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STM32F72xxx STM32F73xxx
(Jun 2018) |
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|
STM32F75xxx STM32F74xxx
(Mar 2018) |
3.3.6 Flash erase sequences |
Current: "2. Set the SER bit and select the sector out of the 8 in the main memory block) wished to erase (SNB) in the FLASH_CR register" Expected: "2. Set the SER bit and select the sector number of the user memory block you wish to erase (SNB) in the FLASH_CR register" |
Jun 2024 |
|
|
STM32F72xxx STM32F73xxx
(Jun 2018) |
||||
|
STM32F72xxx STM32F73xxx
(Jun 2018)
|
Table 11. OTP area organization |
Current: - "OPT14" - "OPT15" Expected: - "OTP14" - "OTP15" |
Jun 2024 |
|
|
STM32F72xxx STM32F73xxx
(Jun 2018) |
Table 3. STM32F72xxx |
Current: "Block base address Expected: "Block base address |
Jun 2024 |
|
|
Table 4. STM32F730xx Flash memory organization |
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|
STM32F413
(May 2018) |
3.6.3 Read protection (RDP) |
Current: "Note: The JTAG port is permanently disabled when Level 2 is active (acting as a JTAG fuse). As a Expected: "Note: The JTAG port is permanently disabled when Level 2 is active (acting as a JTAG fuse). As a |
Jul |
|
|
STM32F413
(May 2018) |
3.8.6 Flash option control register (FLASH_ OPTCR) |
Current: "Reset value: 0x0FFF FFED." Expected: "Reset value: 0x7FFF AAED." |
Aug 2024 |
|
|
STM32H745 (Jun 2023)
STM32H7A3 (Dec 2023)
STM32H742 STM32H743 (Jan 2023)
STM32H723 (Dec 2021)
STM32H7Rx/ RM0477 Rev7 |
FLASH erase operations |
Current: "1. Check and clear (optional) all the error flags due to previous programming/erase Expected: "Remove "optional" word."
|
Aug 2024 |
|
| Table xx. Flash interrupt request |
Expected: Add notes to Clear flag to resume operation for: -Write protection error: Check this flag after an erase operation. -Programming sequence error and Inconsistency error: Check and clear all the (PGSEER, INCERR, STRBERR) error flags due to previous write operation. |
Aug 2024 |
||
|
STM32L4+
(Jun 2021) |
Table 9. Flash module - 1 Mbyte single-bank organization, DB1M = 0 (128 bits read width) |
Current: 
Expected:  |
Sep 2024 |
|
|
STM32L4+
(Jun 2021) |
3.7.8 Flash option register (FLASH_OPTR) |
Current: "Note: For 1-Mbyte and 512-Kbyte Flash memory devices, do not care about Expected: "Note: For 1-Mbyte and 512-Kbyte Flash memory devices, the DBANK option bit must not be used and must be kept at its ST production value of “1”." |
Sep 2024 |
|
| ADC |
STM32F413
(May 2018) |
13.9 Temperature sensor |
Current: "The temperature sensor can be used to measure the ambient temperature (TA) of the device." Expected: "The temperature sensor can be used to measure the junction temperature (TJ) of the device." |
Jun 2024 |
| HRTIM |
STM32G4
(Feb 2024) |
Figure 241. Burst mode emulation example |
Current: 
Expected: |
Mar 2024 |
| TIM |
STM32G4
(Feb 2024) |
Figure 352. Measuring time interval between edges on three signals |
Current: 
Expected: Invert XOR signal |
Mar 2024 |
| USART /UART |
STM32G4
(Feb 2024) |
37.5.7 USART baud rate generation |
Current: Wrong parameter name: "usart_ker_ckpres" Expected: Replace "usart_ker_ckpres" per "usart_ker_ck_pres" |
Mar 2024 |
| LPUART |
STM32L0x3
(Feb 2022) |
Table 150. Error calculation for programmed baud rates at fck = 32 MHz |
Current: Table 150. Error calculation for programmed baud rates at fck = 32 MHz Expected: Table 150. Error calculation for programmed baud rates at fck = 32.768 KHz |
May 2024 |
| RTC |
STM32H523xx
(Apr 2024) |
Table 495. PI8 configuration |
Current: "Table 495. PI8 configuration" Expected: "Table 495. PI8/PB2 configuration" |
Jun 2024 |
| Device electronic signature |
STM32G4 (Feb 2024) |
48.3 Package data register |
Current: 00010: LQFP100 (all devices) and LQFP80 (for category 2 and category 3 devices) Expected: 00010: LQFP100 (all devices) and LQFP80 (for category 2 devices) |
Mar 2024 |
| ETH |
STM32H723
(Dec 2021) |
Table 543. Ethernet peripheral pins |
Current: "ETH_PHY_INTN" Expected: Remove "ETH_PHY_INTN" from Table Ethernet peripheral pins |
Apr 2024 |
|
STM32H742 STM32H743
(Jan 2023) |
Table 522. Ethernet peripheral pins |
Current: "ETH_PHY_INTN" Expected: Remove "ETH_PHY_INTN" from Table Ethernet peripheral pins |
May 2024 |
|
|
STM32H523xx
(Apr 2024)
|
57 Ethernet (ETH): media access control |
Current: Expected:  |
Sep 2024 |
|
| PWR |
STM32U0
(Mar 2024) |
4.4.2 Power control register 2 (PWR_CR2) |
Current: Bit 10 USV(1) Bit 4 PVME1(1) with note "1. Available on STM32U0 devices only." Expected: Bit 10 USV(1) Bit 4 PVME1(1) with note "1. Available on STM32U0x3xx devices only." |
Apr 2024 |
|
STM32F75xxx STM32F74xxx
(Mar 2018) |
4.1.3 Battery backup domain |
Current: If no external battery is used in the application, it is recommended to connect the VBAT pin to VDD with a 100 nF external decoupling ceramic capacitor in parallel. Expected: If no external battery is used in the application, it is recommended to connect VBAT externally to VDD through a 100 nF external ceramic capacitor |
Jun 2024 |
|
|
STM32F72xxx STM32F73xxx
(Jun 2018) |
||||
|
STM32F413
(May 2018) |
5.2.3 Programmable voltage detector (PVD) |
Current: A PVDO flag is available, in the PWR power control/status register (PWR_CSR), to indicate if VDD is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated when VDD drops below the PVD threshold and/or when VDD rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration. As an example the service routine could perform emergency shutdown tasks. Expected: A PVDO flag is available, in the PWR power control/status register (PWR_CSR), to indicate if VDD is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The rising/falling edge sensitivity of the EXTI Line16 should be configured according to PVD output behavior i.e. if the EXTI line 16 is configured to rising edge sensitivity, the interrupt will be generated when VDD drops below the PVD threshold. As an example the service routine could perform emergency shutdown tasks. |
Jul 2024 |
|
|
STM32U0
(Mar 2024) |
4.4.2 Power control register 2 (PWR_CR2) |
Current: "1. Available on STM32U0x3xx devices only." Expected: Remove note "1. Available on STM32U0x3xx devices only." |
Jul 2024 |
|
|
STM32F76xxx STM32F77xxx
(Jul 2024) |
4.3 Low-power modes |
Current: "The MCU exits from Standby low-power mode through an external reset (NRST pin), an IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event occurs" Expected: "The MCU exits from Standby low-power mode through an external reset (NRST pin), an IWDG reset, a rising or falling on one of the enabled WKUPx pins or a RTC event occurs" |
Aug 2024 |
|
|
STM32F75xxx STM32F74xxx
(Jun 2018) |
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|
STM32F72xxx STM32F73xxx
(Jun 2018) |
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| COMP |
STM32F303xB
(Jan 2024) |
17.5.3 COMP3 control and status register (COMP3_CSR)
17.5.4 COMP4 control and status register (COMP4_CSR)
17.5.5 COMP5 control and status register (COMP5_CSR)
17.5.6 COMP6 control and status register (COMP6_CSR)
17.5.7 COMP7 control and status register (COMP7_CSR) |
Current: Bits 3:2 COMPxMODE[1:0]: Comparator x mode (only in STM32F303xB/C and STM32F358xC devices.) Expected: Bits 3:2 COMPxMODE[1:0]: Comparator x mode (only in STM32F303xB/C and STM32F358xC devices.) 00: High speed |
Apr 2024 |
| Documen-tation conven-tions |
STM32G4
(Feb 2024) |
Table 1. STM32G4 series memory density |
Current: 
Expected: |
Mar 2024 |
| DBG |
STM32F413
(May 2018) |
34.16.4 Debug |
Current: Missing "DBG_LPTIM1_STOP" bit description in "DBGMCU_APB1_FZ" register Expected: Add Bit 9 DBG_LPTIM1_STOP: LPTMI1 counter stopped when core is halted |
Jun 2024 |
|
STM32H503
(Mar 2023) |
41.5 ROM tables |
Current: The system ROM table occupies a 4-Kbyte, 32-bit wide chunk of address space, from Expected: The system ROM table occupies a 4-Kbyte, 32-bit wide chunk of address space, from |
Sep 2024 |
|
|
STM32H503
(Mar 2023) |
41.12.4 DBGMCU registers |
Current: They are Expected: They are |
Sep 2024 |
|
| EXTI |
STM32F75xxx STM32F74xxx
(Mar 2018) |
11.9.6 Pending register (EXTI_PR) |
Current: "Reset value: undefined" Expected: "Reset value: 0x0000 0000" |
Jun 2024 |
|
STM32F72xxx STM32F73xxx
(Jun 2018) |
10.9.6 Pending register (EXTI_PR) |
|||
| GPIO |
STM32L41xxx
(Oct 2018) |
8.2 GPIO main features |
Current: • Input states: floating, pull-up/down, analog Expected: • Input states: floating, pull-up/down, analog |
Sep 2024 |
|
8.3 GPIO functional description |
Add section 8.3.4 I/O port state in Low-power modes |
Sep 2024 |
||
| SAI |
STM32H523xx
(Apr 2024) |
53.4.10 PDM interface |
Current: 3. Configure the slot size (DS) to a multiple of (FRL+1). Expected: Remove "3. Configure the slot size (DS) to a multiple of (FRL+1)."
|
Sep 2024 |
| SAES |
STM32H523xx
(Apr 2024) |
34.4.17 SAES key registers |
Current: Repeated writing of KEYSEL[2:0] with the same non-zero value only triggers the loading of DHUK or BHK if KEYVALID is set. Expected: Repeated writing of KEYSEL[2:0] with the same non-zero value only triggers the loading of DHUK or BHK if KEYVALID is cleared. |
Sep 2024 |
| Document Structure |
STM32F72xxx STM32F73xxx
(Jun 2018)
|
- |
Current: In the PDF document: the bookmarks from 1 to 29 are duplicated. Expected: Delete duplicated bookmarks. |
Apr 2024 |
