Introduction
This article includes preliminary updates of STM32 MCU reference manuals reported since 1st January 2024. It highlights the current description requiring update and the expected one if available.
The purpose of this article is to deliver any expected updates to our MCU reference manuals prior to actual documentation releases. We wish to be transparent with our updates and provide them as fast as possible, to assist you in your design process.
This article is updated on a monthly basis. Once these preliminary updates are manifested in the reference manuals, this article is refreshed with new information.
Moving forward, we are also working on providing reference manual releases on a more frequent basis.
IMPORTANT NOTICE - READ CAREFULLY:
- STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to this article at any time without notice.
- Information in this article supersedes and replaces information previously supplied in any prior versions of this article.
- The following table gives a quick reference to the preliminary documentation updates which may be changed or improved without notice.
- This article will be reviewed on a monthly basis and applied updates will be removed from the table.
- The hyperlinks under "Doc Reference - Revision" provides a direct link to the specific document page where the description is located.
Summary of documentation updates : "STM32 MCU reference manuals"
| Function | Series(Lines) / Doc Reference Revision |
Update Location | Current Description / Expected Description |
Date of added update |
| NVIC |
STM32L41xxx STM32L42xxx STM32L43xxx STM32L44xxx STM32L45xxx STM32L46xxx
(Oct 2018) |
Table 46. STM32L41xxx |
Current: Address of RCC and EXTI0 Acronyms is 0x0000 005C Expected: Addresses of RCC and EXTI0 Acronyms are 0x0000 0054 and 0x0000 0058 respectively |
Mar 2024 |
|
Current: "SPI2(4)" with note "4. Not available on STM32L432xx and STM32L442xx devices." Expected: Remove note (4) for SPI2 |
Mar 2024 |
|||
|
Current: "TIM6 global and DAC1(1) underrun interrupts" with note "1. Not available on STM32L41xxx and STM32L42xxx devices." Expected: "TIM6 global and DAC2(5) underrun interrupts" with note"5. Available on STM32L43xxx and STM32L44xxx devices only." |
Mar 2024 |
|||
|
STM32H523xx
(Apr 2024) |
Table 144. STM32H562/ 563/573xx vector table
|
Current: wrong address mapping    Expected:    |
Aug 2024
|
|
|
Table 145. STM32H523/ 533xx vector table
|
Current: wrong address mapping   
Expected:    |
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|
STM32L47xxx, STM32L48xxx, STM32L49xxx STM32L4Axxx
(Oct 2023) |
Table 58. STM32L47x/ |
Current: 4. HASH available on STM32L4Ax devices only. Expected: 4. HASH available on STM32L4Ax devices onlySTM32L4Ax/L49x devices only. |
Oct 2024 |
|
| RCC |
STM32H742 STM32H743 STM32H753 STM32H750
(Jan 2023) |
Table 60. Kernel clock distribution overview |
Current: Maximum allowed frequency [MHz] for ADC1,2,3 are: with note "4. With a duty cycle close to 50%, meaning that DIV[P/Q/R]x values shall be even. For SDMMCx, the duty cycle shall be 50% when supporting DDR." Expected: Maximum allowed frequency [MHz] for ADC1,2,3 are: |
Mar 2024 |
|
STM32F72xxx STM32F73xxx
(Jun 2018) |
5.3.13 RCC APB1 peripheral clock enable register (RCC_ |
Current: "Bit 11 WWDGEN: Window watchdog clock enable Expected: "Bit 11 WWDGEN: Window watchdog clock enable |
Jun 2024 |
|
|
STM32F75xxx STM32F74xxx
(Mar 2018) |
||||
|
STM32F413
(May 2018) |
6.1.1 System reset |
Current: "A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain." Expected: "A system reset sets all registers to their reset values unless specified otherwise in the register description." |
Jul 2024 |
|
|
STM32L41xxx
(Oct 2018)
|
Figure 13. Clock tree |
Current: 
Expected:  |
Sep 2024 |
|
|
STM32L41xxx
(Oct 2018) |
6.2.5 PLL |
Add: PLLP may sometimes be referred to as PLLSAI, as it's primary goal is to be source of audio clock. PLLQ may sometimes be referred to as PLL48M, because it's primary goal is to be source of 48MHz clock. |
Sep 2024 |
|
|
STM32L41xxx
(Oct 2018) |
6.4.27 Peripherals independent clock configuration register (RCC_CCIPR) |
Current: Note: When there is no PLL enabled, the HSI16 clock source is connected automatically to the SAI1 to allow audio detection without the need to turn on the PLL source. Expected: Note: When there is no PLL enabled, the HSI16 clock source is connected automatically to the SAI1 to allow audio detection without the need to turn on the PLL source. |
Sep 2024 |
|
|
STM32H503
(Mar 2023) |
10.4.6 LSE clock |
Current: This external clock is provided to the OSC32_IN pin while the OSC32_OUT pin must be left high-Z Expected: This external clock is provided to the OSC32_IN pin while the OSC32_OUT pin can be used as a GPIO |
Sep 2024 |
|
|
STM32H503
(Mar 2023) |
10.4.10 Clock security system (CSS) |
Current: In addition, the glitches on LSE can be filtered by setting LSEGFON. LSEGFON must be written when the LSE is disabled (LSEON = 0 and LSERDY = 0). Expected: Remove "In addition, the glitches on LSE can be filtered by setting LSEGFON. LSEGFON |
Sep 2024 |
|
|
STM32H523xx STM32H533xx STM32H562xx
RM0481 Rev2 |
11.8.44 RCC kernel clock configuration register (RCC_CCIPR5) |
Current: Bit 3 DACSEL: DAC sample and hold clock Expected: Bit 3 DACSEL: DAC sample and hold clock source selection |
Sep 2024 | |
|
STM32H523xx
RM0481 Rev2 |
11.8.8 RCC PLL clock source selection register (RCC_ PLL2CFGR) |
Current: 0: wide VCO range 192 to 836 MHz (default after reset) Expected: 0: wide VCO range 128 to 560MHz (default after reset) |
Sep 2024 | |
|
STM32H523xx
RM0481 Rev2 |
11.8.13 RCC PLL2 fractional divider register (RCC_ PLL2FRACR) |
Current: * PLL2FRACN can be between 0 and 213- 1 Expected: * FRACN2 can be between 0 and (2^13)-1 |
Sep 2024 | |
|
STM32U5
(Oct 2023) |
11.4.19 OTG_HS clock |
Add sentence Refer to the OTGHSSEL description concerning some limitations that apply when using the PLL as it's input. |
Oct 2024 | |
|
STM32U5
(Oct 2023) |
11.8.47 RCC peripherals independent clock configuration register 2 (RCC_CCIPR2) |
Current: 01: PLL1 “P” (pll1_q_ck) selected, 11: PLL1 “P” divided by 2 (pll1_p_ck/2) selected Expected: 01: PLL1 “P” (pll1_p_ck) selected. If selecting this option, then only HSE input should be selected in PLL1SRC. 11: PLL1 “P” divided by 2 (pll1_p_ck/2) selected. If selecting this option, then only HSE input should be selected in PLL1SRC. |
Oct 2024 | |
|
STM32U5
(Oct 2023)
|
11.8.49 RCC backup domain control register (RCC_BDCR) |
Current: Reset by backup domain reset, except LSCOSEL, LSCOEN, and BDRST that are reset only by backup domain power-on reset. Expected: Reset by backup domain reset, except LSCOSEL, LSCOEN, and BDRST that are reset only by backup domain power-on reset. LSESYSEN and LSESYSRDY are reset by power-on-reset. |
Oct 2024 | |
|
STM32WL33xx
RM0511 Rev1 |
Figure 13. System clock details |
Current: -CK_WDG -CK_MR_SUBGHzWKUP -CK_BUBBLE_WKUP -CLK_BUBBLE Expected: -CLK_WDG -CLK_MR_SUBGHz_WKUP -CLK_LPAWUR_WKUP -CLK_LPAWUR |
Oct 2024 | |
| FLASH |
STM32G4
(Feb 2024) |
Table 28. |
Current: 
Expected: |
Mar 2024 |
|
STM32F75xxx STM32F74xxx
(Mar 2018) |
3.3.7 Flash programming sequences |
Current: "If this cannot be done safely, it is recommended to flush and/or desactivate the ART accelerator by setting respectively the bits ARTRST or ARTEN of the FLASH_CR register" Expected: "If this cannot be done safely, it is recommended to flush and/or desactivate the ART accelerator by setting respectively the bits ARTRST or ARTEN of the FLASH_ACR register" |
Jun 2024 |
|
|
STM32F72xxx STM32F73xxx
(Jun 2018) |
||||
|
STM32F75xxx STM32F74xxx
(Mar 2018) |
3.3.6 Flash erase sequences |
Current: "2. Set the SER bit and select the sector out of the 8 in the main memory block) wished to erase (SNB) in the FLASH_CR register" Expected: "2. Set the SER bit and select the sector number of the user memory block you wish to erase (SNB) in the FLASH_CR register" |
Jun 2024 |
|
|
STM32F72xxx STM32F73xxx
(Jun 2018) |
||||
|
STM32F72xxx STM32F73xxx
(Jun 2018)
|
Table 11. OTP area organization |
Current: - "OPT14" - "OPT15" Expected: - "OTP14" - "OTP15" |
Jun 2024 |
|
|
STM32F72xxx STM32F73xxx
(Jun 2018) |
Table 3. STM32F72xxx |
Current: "Block base address Expected: "Block base address |
Jun 2024 |
|
|
Table 4. STM32F730xx Flash memory organization |
||||
|
STM32F413
(May 2018) |
3.6.3 Read protection (RDP) |
Expected: Adding note: |
Jul |
|
|
STM32F413
(May 2018) |
3.8.6 Flash option control register (FLASH_ OPTCR) |
Current: "Reset value: 0x0FFF FFED." Expected: "Reset value: 0x7FFF AAED." |
Aug 2024 |
|
|
STM32H745 (Jun 2023)
STM32H7A3 (Dec 2023)
STM32H742 STM32H743 (Jan 2023)
STM32H723 (Dec 2021)
STM32H7Rx/ RM0477 Rev7 |
FLASH erase operations |
Current: "1. Check and clear (optional) all the error flags due to previous programming/erase operation. Refer to Section 5.7: FLASH error management for details." Expected: "Remove (optional) word."
|
Aug 2024 |
|
| Table xx. Flash interrupt request |
Expected: Add notes to Clear flag to resume operation for: -Write protection error: Check this flag after an erase operation. -Programming sequence error and Inconsistency error: Check and clear all the (PGSEER, INCERR, STRBERR) error flags due to previous write operation. |
Aug 2024 |
||
|
STM32L4+
(Jun 2021) |
Table 9. Flash module - 1 Mbyte single-bank organization, DB1M = 0 (128 bits read width) |
Current: 
Expected:  |
Sep 2024 |
|
|
STM32L4+
(Jun 2021) |
3.7.8 Flash option register (FLASH_OPTR) |
Current: "Note: For 1-Mbyte and 512-Kbyte Flash memory devices, do not care about DBANK" Expected: "Note: For 1-Mbyte and 512-Kbyte Flash memory devices, the DBANK option bit must not be used and must be kept at its ST production value of “1”." |
Sep 2024 |
|
|
STM32F412
(Oct 2020) |
3.8.6 Flash option control register (FLASH_ OPTCR) |
Current: "Reset value: 0x0FFF FFED." Expected: "Reset value: 0x7FFFAAED "
|
Oct 2024
|
|
|
STM32F410
(Nov 2018) |
||||
| ADC |
STM32F413
(May 2018) |
13.9 Temperature sensor |
Current: "The temperature sensor can be used to measure the ambient temperature (TA) of the device." Expected: "The temperature sensor can be used to measure the junction temperature (TJ) of the device." |
Jun 2024 |
|
STM32F410
(Nov 2018) |
11.9 Temperature sensor |
Oct 2024 |
||
|
STM32F412
(Oct 2020) |
13.9 Temperature sensor |
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|
STM32F401xB
(Dec 2018) |
11.9 Temperature sensor |
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|
STM32U5
(Oct 2023)
|
34.4.28 Battery voltage monitoring |
Current: "As a consequence, the converted digital value is half the VBAT voltage." Expected: "As a consequence, the converted digital value is one fourth of the VBAT voltage" |
Oct 2024 |
|
|
STM32F401xB
(Dec 2018) |
11.3.3 Channel selection |
Current: "Temperature sensor, VREFINT and VBAT internal channels Expected: "Temperature sensor, VREFINT and VBAT internal channels |
Oct 2024 |
|
| HRTIM |
STM32G4
(Feb 2024) |
Figure 241. Burst mode emulation example |
Current: 
Expected: |
Mar 2024 |
| TIM |
STM32G4
(Feb 2024) |
Figure 352. Measuring time interval between edges on three signals |
Current: 
Expected: Invert XOR signal |
Mar 2024 |
|
STM32U5
(Oct 2023) |
54.3.2 TIM1/TIM8 pins and internal signals |
Current: statement before Table 532: "The table below lists the internal sources connected to the tim_etr input multiplexer." Expected: Replace by "The table below lists the internal sources connected to the tim_itr input multiplexer" |
Oct 2024 |
|
| LPTIM |
STM32U5
(Oct 2023) |
Table 598. LPTIM1/2/3/4 external trigger connection |
Current: 
Expected:  |
Oct 2024 |
| USART /UART |
STM32G4
(Feb 2024) |
37.5.7 USART baud rate generation |
Current: Wrong parameter name: "usart_ker_ckpres" Expected: Replace by "usart_ker_ckpres" per "usart_ker_ck_pres" |
Mar 2024 |
| LPUART |
STM32L0x3
(Feb 2022) |
Table 150. Error calculation for programmed baud rates at fck = 32 MHz |
Current: Table 150. Error calculation for programmed baud rates at fck = 32 MHz Expected: Table 150. Error calculation for programmed baud rates at fck = 32.768 KHz |
May 2024 |
| RTC |
STM32H523xx
(Apr 2024) |
Table 495. PI8 configuration |
Current: "Table 495. PI8 configuration" Expected: "Table 495. PI8/PB2 configuration" |
Jun 2024 |
| Device electronic signature |
STM32G4 (Feb 2024) |
48.3 Package data register |
Current: 00010: LQFP100 (all devices) and LQFP80 (for category 2 and category 3 devices) Expected: 00010: LQFP100 (all devices) and LQFP80 (for category 2 devices) |
Mar 2024 |
| ETH |
STM32H723
(Dec 2021) |
Table 543. Ethernet peripheral pins |
Current: "ETH_PHY_INTN" Expected: Remove "ETH_PHY_INTN" from Table Ethernet peripheral pins |
Apr 2024 |
|
STM32H742 STM32H743
(Jan 2023) |
Table 522. Ethernet peripheral pins |
Current: "ETH_PHY_INTN" Expected: Remove "ETH_PHY_INTN" from Table Ethernet peripheral pins |
May 2024 |
|
|
STM32H523xx
(Apr 2024)
|
57 Ethernet (ETH): media access control |
Current: Expected:  |
Sep 2024 |
|
| PWR |
STM32U0
(Mar 2024) |
4.4.2 Power control register 2 (PWR_CR2) |
Current: Bit 10 USV(1) Bit 4 PVME1(1) with note "1. Available on STM32U0 devices only." Expected: Bit 10 USV(1) Bit 4 PVME1(1) with note "1. Available on STM32U0x3xx devices only." |
Apr 2024 |
|
STM32F75xxx STM32F74xxx
(Mar 2018) |
4.1.3 Battery backup domain |
Current: If no external battery is used in the application, it is recommended to connect the VBAT pin to VDD with a 100 nF external decoupling ceramic capacitor in parallel. Expected: If no external battery is used in the application, it is recommended to connect VBAT externally to VDD through a 100 nF external ceramic capacitor |
Jun 2024 |
|
|
STM32F72xxx STM32F73xxx
(Jun 2018) |
||||
|
STM32F413
(May 2018) |
5.2.3 Programmable voltage detector (PVD) |
Current: A PVDO flag is available, in the PWR power control/status register (PWR_CSR), to indicate if VDD is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated when VDD drops below the PVD threshold and/or when VDD rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration. As an example the service routine could perform emergency shutdown tasks. Expected: A PVDO flag is available, in the PWR power control/status register (PWR_CSR), to indicate if VDD is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The rising/falling edge sensitivity of the EXTI Line16 should be configured according to PVD output behavior i.e. if the EXTI line 16 is configured to rising edge sensitivity, the interrupt will be generated when VDD drops below the PVD threshold. As an example the service routine could perform emergency shutdown tasks. |
Jul 2024 |
|
|
STM32U0
(Mar 2024) |
4.4.2 Power control register 2 (PWR_CR2) |
Current: "1. Available on STM32U0x3xx devices only." Expected: Remove note "1. Available on STM32U0x3xx devices only." |
Jul 2024 |
|
|
STM32F76xxx STM32F77xxx
(Jul 2024) |
4.3 Low-power modes |
Current: "The MCU exits from Standby low-power mode through an external reset (NRST pin), an IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event occurs" Expected: "The MCU exits from Standby low-power mode through an external reset (NRST pin), an IWDG reset, a rising or falling on one of the enabled WKUPx pins or a RTC event occurs" |
Aug 2024 |
|
|
STM32F75xxx STM32F74xxx
(Jun 2018) |
||||
|
STM32F72xxx STM32F73xxx
(Jun 2018) |
||||
|
STM32U5
(Oct 2023) |
10.9 PWR interrupts |
Current: "1. The PWR_S3WU interrupt is generated only when the device is in Stop 3 mode (not applicable in Run, Sleep, Stop 0, Stop 1, and Stop 2 modes). " Expected: "1. The PWR_S3WU interrupt is generated only when STOP3 mode is selected (LPMS=011 in PWR_CR1 register, not applicable in Stop 0, Stop 1, and Stop 2 modes)." |
Oct 2024 |
|
|
STM32U5
(Oct 2023) |
10.4.7 Battery backup domain |
Current: "If no external battery is used in the application, it is recommended to connect VBAT externally to VDD with a 100 nF external ceramic decoupling capacitor." Expected: "If no external battery is used in the application, it is recommended to connect VBAT to VDD supply and add a 100 nF ceramic decoupling capacitor on VBAT pin." |
Oct 2024 |
|
|
Current: "Due to the fact that the analog power switch can transfer only a limited amount of current (3 mA), the use of GPIO PC13 to PC15 in output mode is restricted: the speed must be limited to 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (for example to drive a LED)." Expected: "Due to the fact that the analog power switch can transfer only a limited amount of current (3 mA), the use of GPIO PC13 to PC15 in output mode is restricted: the speed must be limited (refer to datasheet for more details) and these I/Os must not be used as a current source (for example to drive a LED)." |
||||
|
STM32L47xxx, STM32L48xxx, STM32L49xxx STM32L4Axxx
(Oct 2023) |
Table 23. Functionalities depending on the working mode |
Current: 5. Not available on STM32L47x/L48x/L49x devices. Expected: 5. Not available on STM32L47x/L48x devices.” |
Oct 2024 |
|
|
STM32L47xxx, STM32L48xxx, STM32L49xxx STM32L4Axxx
(Oct 2023) |
6.4.11 AHB2 peripheral reset register (RCC_ |
Current: Bit 17 HASHRST: Hash reset (this bit is reserved for STM32L47x/L48x/L49x devices) Expected: Bit 17 HASHRST: Hash reset(this bit is reserved for STM32L47x/L48x devices) |
Oct 2024 |
|
|
STM32L47xxx, STM32L48xxx, STM32L49xxx STM32L4Axxx
(Oct 2023) |
6.4.17 AHB2 peripheral clock enable register (RCC_ |
Current: Bit 17 HASHEN: HASH clock enable (this bit is reserved for STM32L47x/L48x/L49x devices) Expected: Bit 17 HASHEN: HASH clock enable (this bit is reserved for STM32L47x/L48x devices) |
Oct 2024 |
|
|
STM32L47xxx, STM32L48xxx, STM32L49xxx STM32L4Axxx
(Oct 2023) |
6.4.23 AHB2 peripheral clocks enable in Sleep and Stop modes register |
Current: Bit 17 HASHSMEN: HASH clock enable during Sleep and Stop modes (this bit is reserved for STM32L47x/L48x/L49x devices) Expected: Bit 17 HASHEN: HASH clock enable (this bit is reserved for STM32L47x/L48x devices) |
Oct 2024 |
|
|
STM32F410
(Nov 2018) |
Table 22. PWR - register map and reset values |
Current: VOS[1:0] = 11b Expected: VOS[1:0] = 10b |
Oct 2024
|
|
|
STM32F401xB
(Dec 2018) |
Table 21. PWR - register map and reset values |
|||
| PWRC |
STM32WL33xx
RM0511 Rev1 |
5 Power controller (PWRC) |
Current: "SPMS" Expected: "SMPS" |
Oct 2024 |
| COMP |
STM32F303xB
(Jan 2024) |
17.5.3 COMP3 control and status register (COMP3_CSR)
17.5.4 COMP4 control and status register (COMP4_CSR)
17.5.5 COMP5 control and status register (COMP5_CSR)
17.5.6 COMP6 control and status register (COMP6_CSR)
17.5.7 COMP7 control and status register (COMP7_CSR) |
Current: Bits 3:2 COMPxMODE[1:0]: Comparator x mode (only in STM32F303xB/C and STM32F358xC devices.) Expected: Bits 3:2 COMPxMODE[1:0]: Comparator x mode (only in STM32F303xB/C and STM32F358xC devices.) 00: High speed |
Apr 2024 |
| Documen-tation conven-tions |
STM32G4
(Feb 2024) |
Table 1. STM32G4 series memory density |
Current: 
Expected: |
Mar 2024 |
| DBG |
STM32F413
(May 2018) |
34.16.4 Debug |
Current: Missing "DBG_LPTIM1_STOP" bit description in "DBGMCU_APB1_FZ" register Expected: Add Bit 9 DBG_LPTIM1_STOP: LPTMI1 counter stopped when core is halted
|
Jun 2024 |
|
STM32F410
(Nov 2018)
|
26.16.4 Debug MCU APB1 freeze register (DBGMCU_ |
Oct 2024 |
||
|
STM32H503
(Mar 2023) |
41.5 ROM tables |
Current: The system ROM table occupies a 4-Kbyte, 32-bit wide chunk of address space, from 0xE00E 0000 to 0xE00E 0FFC, when accessed by the debugger. It can be accessed by the CPU at the address range 0x4402 0000 to 0x4402 0FFC. Expected: The system ROM table occupies a 4-Kbyte, 32-bit wide chunk of address space, from 0xE00E 4000 to 0xE00E 4FFC, when accessed by the debugger. It can be accessed by the CPU at the address range 0x4402 4000 to 0x4402 4FFC. |
Sep 2024 |
|
|
STM32H503
(Mar 2023) |
41.12.4 DBGMCU registers |
Current: They are accessible to the debugger via the AHB access port at base address 0xE004 4000, and to software at base address 0x4402 4000. Expected: They are accessible to the debugger via the AHB access port at base address 0xE00E 4000, and to software at base address 0x4402 4000 |
Sep 2024 |
|
|
STM32U5
(Oct 2023) |
75.8.1 BPU registers |
Current: Bit 1 KEY: Write protect key Expected: Bit 1 KEY: Write protect key |
Oct 2024 |
|
|
STM32U5
(Oct 2023) |
75.9.1 ETM registers |
Current: Bits 11:0 CCITMIN[11:0]: minimum value that can be programmed to TRCCCCTLR. Expected: Bits 11:0 CCITMIN[11:0]: minimum value that can be programmed to ETM_CCCTLR. |
Oct 2024 |
|
|
STM32U5
(Oct 2023) |
75.12.4 DBGMCU registers |
Current: For STM32U575/585 Expected: For STM32U575/585 |
Oct 2024 |
|
|
STM32F412
(Oct 2020) |
30.6.1 MCU device ID code |
Current: Bits 31:16 REV_ID(15:0): Revision identifier Expected: Bits 31:16 REV_ID(15:0): Revision identifier |
Oct 2024 |
|
|
STM32F410
(Nov 2018) |
26.6.1 MCU device ID code |
Current: Bits 31:16 REV_ID(15:0) Revision identifier Expected: Bits 31:16 REV_ID(15:0): Revision identifier |
Oct 2024 |
|
|
STM32F401xB
(Dec 2018) |
23.6.1 MCU device ID code |
Current: Bits 31:16 REV_ID[15:0] Revision identifier Expected: Bits 31:16 REV_ID(15:0): Revision identifier |
Oct 2024 |
|
| EXTI |
STM32F75xxx STM32F74xxx
(Mar 2018) |
11.9.6 Pending register (EXTI_PR) |
Current: "Reset value: undefined" Expected: "Reset value: 0x0000 0000" |
Jun 2024 |
|
STM32F72xxx STM32F73xxx
(Jun 2018) |
10.9.6 Pending register (EXTI_PR) |
|||
| GPIO |
STM32L41xxx
(Oct 2018) |
8.2 GPIO main features |
Current: • Input states: floating, pull-up/down, analog Expected: • Input states: floating, pull-up/down, analog |
Sep 2024 |
|
STM32L41xxx
(Oct 2018) |
8.4 GPIO functional description |
Add section 8.3.4 I/O port state in Low-power modes |
Sep 2024 |
|
|
STM32L47xxx, STM32L48xxx, STM32L49xxx STM32L4Axxx
(Oct 2023) |
Oct 2024 |
|||
|
STM32U5
(Oct 2023) |
13.3.12 Analog configuration
|
Current: The weak pull-up and pull-down resistors are disabled by hardware. Expected: The weak pull-up is disabled by hardware. The weak pull-down is configurable. |
Oct 2024 |
|
|
STM32U5
(Oct 2023) |
13.3.20 High-speed low-voltage mode (HSLV) |
Add sentence Caution: Setting this bit when the I/O is configured in Fm+ mode is forbidden. An I/O is in Fm+ mode when it is configured as I2C alternate function, with FMP=1 in I2C_CR1 register. PB6, PB7, PB6, PB9 can also be in Fm+ mode when PB6_FMP, PB7_FMP, PB8_FMP, PB9_FMP, respectively, is set in SYSCFG_CFGR1 register. |
Oct 2024 |
|
|
STM32U5
(Oct 2023) |
13.4.12 GPIO high-speed low-voltage register (GPIOx_ HSLVR) (x = A to J) |
Current: Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Expected: Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be |
Oct 2024 |
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|
STM32U5
(Oct 2023) |
13.3.2 I/O pin alternate function multiplexer and mapping |
Add sentence - Cortex-M33 alternate function (EVENTOUT) |
Oct 2024 |
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|
STM32L47xxx, STM32L48xxx, STM32L49xxx STM32L4Axxx
(Oct 2023) |
8.2 GPIO main features |
Add sentence Configurable state of each I/O in Standby mode: floating, pull-up/down, analog. |
Oct 2024 |
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|
STM32F410
(Nov 2018) |
6.3.2 I/O pin multiplexer and mapping |
Current: Cortex®-M4 with FPU EVENTOUT is mapped on AF15. Expected: Cortex®-M4 with FPU output EVENTOUT signal can be used by configuring the I/O pin to output on AF15. |
Oct 2024 |
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STM32F401xB
(Dec 2018) |
8.3.2 I/O pin multiplexer and mapping | |||
| SAI |
STM32H523xx
(Apr 2024) |
53.4.10 PDM interface |
Current: 3. Configure the slot size (DS) to a multiple of (FRL+1). Expected: Remove "3. Configure the slot size (DS) to a multiple of (FRL+1)." |
Sep 2024 |
| DMA |
STM32L47xxx, STM32L48xxx, STM32L49xxx STM32L4Axxx
(Oct 2023) |
Table 43. DMA1 and DMA2 implementation |
Current: 1. HASH related DMA channel is only applicable for STM32L4Ax devices. Expected: 1. HASH related DMA channel is only applicable for STM32L4Ax/L49x devices. |
Oct 2024 |
|
STM32L47xxx, STM32L48xxx, STM32L49xxx STM32L4Axxx
(Oct 2023) |
Table 45. DMA2 requests for each channel Figure 31. DMA block diagram |
Current: "3. Only available on STM32L4Ax devices." Expected: "3. Only available on STM32L4Ax/L49x devices." |
Oct 2024 |
|
|
STM32F410
(Nov 2018) |
Table 29. DMA1 request mapping |
Current: "DAC2 interface (on Stream 6 of Channel 7)." Expected: Remove "DAC2 interface (on Stream 6 of Channel 7)." |
Oct 2024 |
|
| DAC |
STM32F410
(Nov 2018) |
Figure 40. DAC channel block diagram 12.3 DAC output buffer enable |
Current: Several name used "DAC_OUT1", "DAC1_OUT", and "DAC1_OUT1" Expected: Use a single name "DAC_OUT" |
Oct 2024 |
| DFSDM |
STM32F412
(Oct 2020)
|
14.4.3 DFSDM reset and clocks |
Current: "Audio clock source is SAI1 clock selected by SAI1SEL[1:0] field in RCC configuration" Expected: Remove "Audio clock source is SAI1 clock selected by SAI1SEL[1:0] field in RCC configuration" |
Oct 2024 |
| SAES |
STM32H523xx
(Apr 2024) |
34.4.17 SAES key registers |
Current: Repeated writing of KEYSEL[2:0] with the same non-zero value only triggers the loading of DHUK or BHK if KEYVALID is set. Expected: Repeated writing of KEYSEL[2:0] with the same non-zero value only triggers the loading of DHUK or BHK if KEYVALID is cleared. |
Sep 2024 |
| DSI |
STM32U5
(Oct 2023)
|
44.15.6 DSI Host LTDC polarity configuration register (DSI_LPCR) |
Current: Bit 2 HSP: HSYNC polarity Bit 1 VSP: VSYNC polarity Expected: Bit 2 HSP: HSYNC polarity |
Oct 2024 |
| HSPI |
STM32U5
(Oct 2023) |
30.7.3 HSPI device configuration register 2 (HSPI_DCR2) |
Current: Writing this bitfield automatically starts a new calibration of high-speed interface DLL Expected: Writing this bitfield automatically starts a new calibration of high-speed interface DLL |
Oct 2024 |
| SYSCFG |
STM32U5
(Oct 2023) |
15.3.2 SYSCFG configuration register 1 (SYSCFG_ |
Current: - 0: I/O analog switches are supplied by VDDA or booster when booster is ON. - Bit 8 BOOSTEN: I/O analog switch voltage booster enable - The table below describes when bit 8 (BOOSTEN) and bit 9 (ANASWVDD) must be set or reset depending on the voltage settings. Expected: 0: If booster if OFF: I/O analog switches are supplied by VDDA if ASV=1 in PWR_SVMCR, by VDD if ASV=0. If booster is ON: I/O analog switches are supplied by booster. - Bit 8 BOOSTEN: I/O analog switch voltage booster enable. This bit has only effect when ASV=1 in PWR_SVMR, and ANASWVDD=0. -The table below describes when bit 8 (BOOSTEN) and bit 9 (ANASWVDD) must be set or reset depending on the voltage settings. When VDDA voltage is lower than 2.4 V and VDD is higher than 2.4 V, the I/O analog switch must be powered by VDD. When both VDD and VDDA voltages are lower than 2.4 V, the I/O analog switch must be powered by the output of the VDD booster. When I/O analog switches are supplied by VDDA or VDD booster, ASV must be set to 1 in PWR_SVMCR. |
Oct 2024 |
| Hash |
STM32L47xxx, STM32L48xxx, STM32L49xxx STM32L4Axxx
(Oct 2023) |
29 Hash processor (HASH) |
Current: This section applies to STM32L4Ax devices only. Expected: This section applies to STM32L4Ax/L49x devices only. |
Oct 2024 |
| LPAWUR |
STM32WL33xx
RM0511 Rev1 |
28.3.3 Frame format |
Current: The payload of the specific Wakeup frame has a static length of 8 bytes (56 bits), Expected: The payload of the specific Wakeup frame has a static length of maximum 8 bytes (56 bits by default) |
Oct 2024 |
