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Laurids_PETERSE
Introduction
This article includes preliminary updates of STM32 MCU reference manuals reported since 1st January 2024. It highlights the current description requiring update and the expected one if available.
The purpose of this article is to deliver any expected updates to our MCU reference manuals prior to actual documentation releases. We wish to be transparent with our updates and provide them as fast as possible, to assist you in your design process.
This article is updated on a monthly basis. Once these preliminary updates are manifested in the reference manuals, this article is refreshed with new information.
Moving forward, we are also working on providing reference manual releases on a more frequent basis.
IMPORTANT NOTICE - READ CAREFULLY:
- STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to this article at any time without notice.
- Information in this article supersedes and replaces information previously supplied in any prior versions of this article.
- The following table gives a quick reference to the preliminary documentation updates which may be changed or improved without notice.
- This article will be reviewed on a monthly basis and applied updates will be removed from the table.
- The hyperlinks under "Doc Reference - Revision" provides a direct link to the specific document page where the description is located.
Summary of documentation updates: "STM32 MCU reference manuals"
| Function | Series(Lines) / Doc Reference Revision |
Update Location | Current Description / Expected Description |
Date of added update |
| NVIC |
STM32H523xx
(Apr 2024) |
Table 144. STM32H562/ 563/573xx vector table
|
Current: Wrong address mapping. Expected:    |
Aug 2024
|
|
Table 145. STM32H523/ 533xx vector table
|
Current: Wrong address mapping. Expected:    |
|||
|
STM32L47xxx, STM32L48xxx, STM32L49xxx STM32L4Axxx
(Oct 2023) |
Table 58. STM32L47x/ |
Current: 4. HASH available on STM32L4Ax devices only. Expected: 4. HASH available on STM32L4Ax devices onlySTM32L4Ax/L49x devices only. |
Oct 2024 |
|
| RCC |
STM32H742 STM32H743 STM32H753 STM32H750
(Jan 2023) |
Table 60. Kernel clock distribution overview |
Current: Maximum allowed frequency [MHz] for ADC1,2,3 are: with note "4. With a duty cycle close to 50%, meaning that DIV[P/Q/R]x values shall be even. For SDMMCx, the duty cycle shall be 50% when supporting DDR." Expected: Maximum allowed frequency [MHz] for ADC1,2,3 are: |
Mar 2024 |
|
STM32F72xxx STM32F73xxx
(Jun 2018) |
5.3.13 RCC APB1 peripheral clock enable register (RCC_ |
Current: "Bit 11 WWDGEN: Window watchdog clock enable Expected: "Bit 11 WWDGEN: Window watchdog clock enable |
Jun 2024 |
|
|
STM32F75xxx STM32F74xxx
(Mar 2018) |
||||
|
STM32H523xx STM32H533xx STM32H562xx
RM0481 Rev2 |
11.8.44 RCC kernel clock configuration register (RCC_CCIPR5) |
Current: Bit 3 DACSEL: DAC sample and hold clock Expected: Bit 3 DACSEL: DAC sample and hold clock source selection |
Sep 2024 | |
|
STM32H523xx
RM0481 Rev2 |
11.8.8 RCC PLL clock source selection register (RCC_ PLL2CFGR) |
Current: 0: wide VCO range 192 to 836 MHz (default after reset) Expected: 0: wide VCO range 128 to 560MHz (default after reset) |
Sep 2024 | |
|
STM32H523xx
RM0481 Rev2 |
11.8.13 RCC PLL2 fractional divider register (RCC_ PLL2FRACR) |
Current: * PLL2FRACN can be between 0 and 213- 1 Expected: * FRACN2 can be between 0 and (2^13)-1 |
Sep 2024 | |
|
STM32U5
(Oct 2023) |
11.4.19 OTG_HS clock |
Add sentence Refer to the OTGHSSEL description concerning some limitations that apply when using the PLL as it's input. |
Oct 2024 | |
|
STM32U5
(Oct 2023) |
11.8.47 RCC peripherals independent clock configuration register 2 (RCC_CCIPR2) |
Current: 01: PLL1 “P” (pll1_q_ck) selected, 11: PLL1 “P” divided by 2 (pll1_p_ck/2) selected Expected: 01: PLL1 “P” (pll1_p_ck) selected. If selecting this option, then only HSE input should be selected in PLL1SRC. 11: PLL1 “P” divided by 2 (pll1_p_ck/2) selected. If selecting this option, then only HSE input should be selected in PLL1SRC. |
Oct 2024 | |
|
STM32U5
(Oct 2023) |
11.8.49 RCC backup domain control register (RCC_BDCR) |
Current: Reset by backup domain reset, except LSCOSEL, LSCOEN, and BDRST that are reset only by backup domain power-on reset. Expected: Add: LSESYSEN and LSESYSRDY are reset by power-on-reset. |
Oct 2024 | |
|
STM32H723 (Dec 2021) |
8.7.39 RCC AHB3 clock register (RCC_ AHB3ENR) |
Expected:  |
Dec 2024 | |
|
STM32H723 (Dec 2021) |
8.7.28 RCC AHB1 peripheral reset register(RCC_ AHB1RSTR) |
Current: Bit 1 DMA2RST: DMA2 block reset Expected: Bit 1 DMA2RST: DMA2 and DMAMUX1 reset |
Dec 2024 | |
|
STM32H723 (Dec 2021) |
8.7.30 RCC AHB4 peripheral reset register (RCC_ AHB4RSTR) |
Current: Bit 21 BDMARST: BDMA block reset Expected: Bit 21 BDMARST: BDMA block reset |
Dec 2024 | |
|
STM32U0
(Mar 2024) |
5.2.6 LSE clock |
Expected: Add: Distribution of the LSE clock out of RTC block is gated by default to achieve lowest power consumption. Set LSESYSEN bit in the RCC-BDCR to release clock distribution to LCD, SYSCLK, LSCO and MCO. |
Dec 2024 | |
|
STM32U0
(Mar 2024) |
5.4.22 RTC domain control register (RCC_BDCR) |
Current: Bit 2 LSEBYP: LSE oscillator bypass Expected: Bit 2 LSEBYP: LSE oscillator bypass |
Dec 2024 | |
|
STM32G4
(Feb 2024) |
7.1.2 System reset |
Current: A system reset sets all registers to their reset values except the reset flags in the clock control/status register (RCC_CSR) and the registers in the RTC domain. Expected: A system reset sets all registers to their reset values unless specified otherwise in the register description. |
Dec 2024 | |
|
STM32G4
(Feb 2024) |
7.2.7 System clock (SYSCLK) selection |
Current: Status bits in the Internal clock sources calibration register (RCC_ICSCR) indicate which clock(s) is (are) ready and which clock is currently used as a system clock. Expected: Status bits in the RCC_CR and RCC_CFGR registers indicate which clock(s) is (are) ready and which clock is currently used as a system clock. |
Dec 2024 | |
|
STM32G4
(Feb 2024) |
7.4.6 Clock interrupt flag register (RCC_CIFR) |
Current: - PLLRDYDIE Expected: - PLLRDYIE |
Dec 2024 | |
| FLASH |
STM32G4
(Feb 2024) |
Table 28. |
Expected: |
Mar 2024 |
|
STM32F75xxx STM32F74xxx
(Mar 2018) |
3.3.7 Flash programming sequences |
Current: "If this cannot be done safely, it is recommended to flush and/or desactivate the ART accelerator by setting respectively the bits ARTRST or ARTEN of the FLASH_CR register" Expected: "If this cannot be done safely, it is recommended to flush and/or desactivate the ART accelerator by setting respectively the bits ARTRST or ARTEN of the FLASH_ACR register" |
Jun 2024 |
|
|
STM32F72xxx STM32F73xxx
(Jun 2018) |
||||
|
STM32F75xxx STM32F74xxx
(Mar 2018) |
3.3.6 Flash erase sequences |
Current: "2. Set the SER bit and select the sector out of the 8 in the main memory block) wished to erase (SNB) in the FLASH_CR register" Expected: "2. Set the SER bit and select the sector number of the user memory block you wish to erase (SNB) in the FLASH_CR register" |
Jun 2024 |
|
|
STM32F72xxx STM32F73xxx
(Jun 2018) |
||||
|
STM32F72xxx STM32F73xxx
(Jun 2018)
|
Table 11. OTP area organization |
Current: - "OPT14" - "OPT15" Expected: - "OTP14" - "OTP15" |
Jun 2024 |
|
|
STM32F72xxx STM32F73xxx
(Jun 2018) |
Table 3. STM32F72xxx |
Current: "Block base address on ICTM interface" Expected: "Block base address on ITCM interface" |
Jun 2024 |
|
|
Table 4. STM32F730xx Flash memory organization |
||||
|
STM32H745 (Jun 2023)
STM32H7A3 (Dec 2023)
STM32H742 STM32H743 (Jan 2023)
STM32H723 (Dec 2021)
STM32H7Rx/ RM0477 Rev8 |
FLASH erase operations |
Current: "1. Check and clear (optional) all the error flags due to previous programming/erase operation. Refer to Section 5.7: FLASH error management for details." Expected: "Remove (optional) word."
|
Aug 2024 |
|
| Table xx. Flash interrupt request |
Expected: Add notes to Clear flag to resume operation for: -Write protection error: Check this flag after an erase operation. -Programming sequence error and Inconsistency error: Check and clear all the (PGSEER, INCERR, STRBERR) error flags due to previous write operation. |
Aug 2024 |
||
|
STM32L4+
(Jun 2021) |
Table 9. Flash module - 1 Mbyte single-bank organization, DB1M = 0 (128 bits read width) |
Expected:  |
Sep 2024 |
|
|
STM32L4+
(Jun 2021) |
3.7.8 Flash option register (FLASH_OPTR) |
Current: "Note: For 1-Mbyte and 512-Kbyte Flash memory devices, do not care about DBANK" Expected: "Note: For 1-Mbyte and 512-Kbyte Flash memory devices, the DBANK option bit must not be used and must be kept at its ST production value of “1”." |
Sep 2024 |
|
|
STM32F412
(Oct 2020) |
3.8.6 Flash option control register (FLASH_ OPTCR) |
Current: "Reset value: 0x0FFF FFED." Expected: "Reset value: 0x7FFFAAED " |
Oct 2024
|
|
|
STM32F410
(Nov 2018) |
||||
|
STM32G4
(Feb 2024) |
3.4.2 Option bytes programming |
Expected: Add "Flash securable area bank1 register (FLASH_SEC1R), Flash securable area bank2 register (FLASH_SEC2R)" in 3. Write the desired options value in the options registers step |
Nov 2024 |
|
|
STM32G4
(Feb 2024) |
4.4.2 Option bytes programming |
Expected: Add "Flash securable area bank1 register (FLASH_SEC1R)" in 3. Write the desired options value in the options registers step |
Nov 2024 |
|
| 5.4.2 Option bytes programming | ||||
|
STM32G4
(Feb 2024)
|
3 Embedded flash memory (FLASH) for category 3 devices 4 Embedded flash memory (FLASH) for category 4 devices 5 Embedded flash memory (FLASH) for category 2 devices |
Current: "Reserved, must be kept at reset value." Expected: "Reserved, should be set to 1 during option bytes programming." |
Nov 2024 |
|
|
STM32G4
(Feb 2024) |
4.7.13 Flash securable area register (FLASH_ |
Current: Bit 16 BOOT_LOCK: used to force boot from user flash area Expected: Add: This bit can only be changed in RDP level 0 or when doing regression from RDP level 1 to RDP level 0. |
Nov 2024 |
|
|
STM32WBA5
(Sep 2024) |
7.3.2 Error code correction (ECC) |
Expected: Add: The following addresses in the Flash system memory are used to store words including - 0x0BF9 1F80 embeds a word with 2-bit errors |
Nov 2024 |
|
| ADC |
STM32F410
(Nov 2018) |
11.9 Temperature sensor |
Current: "The temperature sensor can be used to measure the ambient temperature (TA) of the device." Expected: "The temperature sensor can be used to measure the junction temperature (TJ) of the device." |
Oct 2024 |
|
STM32F412
(Oct 2020) |
13.9 Temperature sensor |
|||
|
STM32F401xB
(Dec 2018) |
11.9 Temperature sensor |
|||
|
STM32U5
(Oct 2023)
|
34.4.28 Battery voltage monitoring |
Current: "As a consequence, the converted digital value is half the VBAT voltage." Expected: "As a consequence, the converted digital value is one fourth of the VBAT voltage" |
Oct 2024 |
|
|
STM32F401xB
(Dec 2018) |
11.3.3 Channel selection |
Current: • The temperature sensor is internally connected to ADC1_IN18 channel which is shared with VBAT. Only one conversion, temperature sensor or VBAT, must be selected at a time. When the temperature sensor and VBAT conversion are set simultaneously, only the VBAT conversion is performed. Expected:• The temperature sensor is internally connected to ADC1_IN18 and ADC1_IN16 channels which is shared with VBAT. Only one conversion, temperature sensor or VBAT, must be selected at a time. When the temperature sensor and VBAT conversion are set simultaneously, only the VBAT conversion is performed. |
Oct 2024 |
|
| HRTIM |
STM32G4
(Feb 2024) |
Figure 241. Burst mode emulation example |
Expected: |
Mar 2024 |
| TIM |
STM32G4
(Feb 2024) |
Figure 352. Measuring time interval between edges on three signals |
Expected: Invert XOR signal |
Mar 2024 |
|
STM32U5
(Oct 2023) |
54.3.2 TIM1/TIM8 pins and internal signals |
Current: statement before Table 532: "The table below lists the internal sources connected to the tim_etr input multiplexer." Expected: Replace by "The table below lists the internal sources connected to the tim_itr input multiplexer" |
Oct 2024 |
|
|
STM32F401xB
(Dec 2018) |
12.4.9 TIM1 capture/ compare enable register (TIMx_CCER) |
Current: Bits 15:14 Reserved, must be kept at reset value. Expected: Bit 15 CC4NP: Capture/Compare 4 complementary output polarity refer to CC1NP description |
Dec 2024 |
|
|
STM32F469xx STM32F479xx (May 2024) |
22.4.9 TIM1&TIM8 capture/ |
|||
|
STM32F410
(Nov 2018) |
14.4.9 TIM1 capture/ |
|||
|
STM32F412
(Oct 2020) |
16.4.9 TIM1&TIM8 capture/ |
|||
|
STM32F413 (Oct 2024) |
17.4.9 TIM1&TIM8 capture/ |
|||
|
STM32F410
(Nov 2018) |
15.3.11 Encoder interface mode |
Current: CC2S= ‘01’ (TIMx_CCMR2 register, TI2FP2 mapped on TI2) Expected: CC2S= ‘01’ (TIMx_CCMR1 register, TI2FP2 mapped on TI2) |
Dec 2024 |
|
|
STM32H723 (Dec 2021) |
44.3.11 Combined PWM mode |
Current: When a given channel is used as combined PWM channel, its secondary channel must be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the other in Combined PWM mode 2) Expected: When a given channel is used as combined PWM channel, its secondary channel must be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the other in PWM mode 2) |
Dec 2024 |
|
| LPTIM |
STM32U5
(Oct 2023) |
Table 598. LPTIM1/2/3/4 external trigger connection |
Current: "lpdma_ch1_tc"Expected: "lpdma_ch0_tc" |
Oct 2024 |
| USART /UART |
STM32G4
(Feb 2024) |
37.5.7 USART baud rate generation |
Current: Wrong parameter name: "usart_ker_ckpres" Expected: "usart_ker_ck_pres" |
Mar 2024 |
| LPUART |
STM32L0x3
(Feb 2022) |
Table 150. Error calculation for programmed baud rates at fck = 32 MHz |
Current: Table 150. Error calculation for programmed baud rates at fck = 32 MHz Expected: Table 150. Error calculation for programmed baud rates at fck = 32.768 KHz |
May 2024 |
| RTC |
STM32H523xx
(Apr 2024) |
Table 495. PI8 configuration |
Current: "Table 495. PI8 configuration" Expected: "Table 495. PI8/PB2 configuration" |
Jun 2024 |
| Device electronic signature |
STM32G4 (Feb 2024) |
48.3 Package data register |
Current: 00010: LQFP100 (all devices) and LQFP80 (for category 2 and category 3 devices) Expected: 00010: LQFP100 (all devices) and LQFP80 (for category 2 devices) |
Mar 2024 |
| ETH |
STM32H723
(Dec 2021) |
Table 543. Ethernet peripheral pins |
Expected: Remove "ETH_PHY_INTN" from Table Ethernet peripheral pins |
Apr 2024 |
|
STM32H742 STM32H743
(Jan 2023) |
Table 522. Ethernet peripheral pins |
Current: "ETH_PHY_INTN" Expected: Remove "ETH_PHY_INTN" from Table Ethernet peripheral pins |
May 2024 |
|
|
STM32H523xx
(Apr 2024)
|
57 Ethernet (ETH): media access control |
Expected:  |
Sep 2024 |
|
| PWR |
STM32U0
(Mar 2024) |
4.4.2 Power control register 2 (PWR_CR2) |
Current: Bit 10 USV(1) Bit 4 PVME1(1) with note "1. Available on STM32U0 devices only." Expected: Bit 10 USV(1) Bit 4 PVME1(1) with note "1. Available on STM32U0x3xx devices only." |
Apr 2024 |
|
STM32F75xxx STM32F74xxx
(Mar 2018) |
4.1.3 Battery backup domain |
Current: If no external battery is used in the application, it is recommended to connect the VBAT pin to VDD with a 100 nF external decoupling ceramic capacitor in parallel. Expected: If no external battery is used in the application, it is recommended to connect VBAT externally to VDD through a 100 nF external ceramic capacitor |
Jun 2024 |
|
|
STM32F72xxx STM32F73xxx
(Jun 2018) |
||||
|
STM32U0
(Mar 2024) |
4.4.2 Power control register 2 (PWR_CR2) |
Current: "1. Available on STM32U0x3xx devices only." Expected: Remove note "1. Available on STM32U0x3xx devices only." |
Jul 2024 |
|
|
STM32F76xxx STM32F77xxx
(Jul 2024) |
4.3 Low-power modes |
Current: "The MCU exits from Standby low-power mode through an external reset (NRST pin), an IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event occurs" Expected: "The MCU exits from Standby low-power mode through an external reset (NRST pin), an IWDG reset, a rising or falling on one of the enabled WKUPx pins or a RTC event occurs" |
Aug 2024 |
|
|
STM32F75xxx STM32F74xxx
(Jun 2018) |
||||
|
STM32F72xxx STM32F73xxx
(Jun 2018) |
||||
|
STM32U5
(Oct 2023) |
10.9 PWR interrupts |
Current: "1. The PWR_S3WU interrupt is generated only when the device is in Stop 3 mode (not applicable in Run, Sleep, Stop 0, Stop 1, and Stop 2 modes). " Expected: "1. The PWR_S3WU interrupt is generated only when STOP3 mode is selected (LPMS=011 in PWR_CR1 register, not applicable in Stop 0, Stop 1, and Stop 2 modes)." |
Oct 2024 |
|
|
STM32U5
(Oct 2023) |
10.4.7 Battery backup domain |
Current: "If no external battery is used in the application, it is recommended to connect VBAT externally to VDD with a 100 nF external ceramic decoupling capacitor." Expected: "If no external battery is used in the application, it is recommended to connect VBAT to VDD supply and add a 100 nF ceramic decoupling capacitor on VBAT pin." |
Oct 2024 |
|
|
Current: "Due to the fact that the analog power switch can transfer only a limited amount of current (3 mA), the use of GPIO PC13 to PC15 in output mode is restricted: the speed must be limited to 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (for example to drive a LED)." Expected: "Due to the fact that the analog power switch can transfer only a limited amount of current (3 mA), the use of GPIO PC13 to PC15 in output mode is restricted: the speed must be limited (refer to datasheet for more details) and these I/Os must not be used as a current source (for example to drive a LED)." |
||||
|
STM32L47xxx STM32L48xxx STM32L49xxx STM32L4Axxx
(Oct 2023) |
Table 23. Functionalities depending on the working mode |
Current: 5. Not available on STM32L47x/L48x/L49x devices. Expected: 5. Not available on STM32L47x/L48x devices.” |
Oct 2024 |
|
|
STM32L47xxx STM32L48xxx STM32L49xxx STM32L4Axxx
(Oct 2023) |
6.4.11 AHB2 peripheral reset register (RCC_ |
Current: Bit 17 HASHRST: Hash reset (this bit is reserved for STM32L47x/L48x/L49x devices) Expected: Bit 17 HASHRST: Hash reset(this bit is reserved for STM32L47x/L48x devices) |
Oct 2024 |
|
|
STM32L47xxx STM32L48xxx STM32L49xxx STM32L4Axxx
(Oct 2023) |
6.4.17 AHB2 peripheral clock enable register (RCC_ |
Current: Bit 17 HASHEN: HASH clock enable (this bit is reserved for STM32L47x/L48x/L49x devices) Expected: Bit 17 HASHEN: HASH clock enable (this bit is reserved for STM32L47x/L48x devices) |
Oct 2024 |
|
|
STM32L47xxx, STM32L48xxx, STM32L49xxx STM32L4Axxx
(Oct 2023) |
6.4.23 AHB2 peripheral clocks enable in Sleep and Stop modes register |
Current: Bit 17 HASHSMEN: HASH clock enable during Sleep and Stop modes (this bit is reserved for STM32L47x/L48x/L49x devices) Expected: Bit 17 HASHEN: HASH clock enable (this bit is reserved for STM32L47x/L48x devices) |
Oct 2024 |
|
|
STM32F410
(Nov 2018) |
Table 22. PWR - register map and reset values |
Current: VOS[1:0] = 11b Expected: VOS[1:0] = 10b |
Oct 2024
|
|
|
STM32F401xB
(Dec 2018) |
Table 21. PWR - register map and reset values |
|||
|
STM32U5
(Oct 2023) |
10.4.7 Battery backup domain |
Expected: 10.4.7Battery backup domain (also known as RTC domain)
|
Nov 2024 |
|
|
STM32L47xxx, STM32L48xxx, STM32L49xxx STM32L4Axxx (Oct 2023) |
5.3.10 Shutdown mode |
Current: Exiting Shutdown mode Expected: Add WUFx bits in the PWR_SR1 register are cleared by power-on reset during Shutdown mode exit. They will be seen as set only if the related wake-up signal is longer than release of the power-on reset signal. |
Dec 2024
|
|
|
STM32U0
(Mar 2024) |
4.3.10 Shutdown mode |
|||
|
STM32U0
(Mar 2024) |
Table 30. Shutdown mode |
Current: WKUPx pin edge, RTC event, external Reset in NRST pin Expected: WKUPx pin edge, RTC event, TAMP event, external Reset on NRST pin |
Dec 2024 |
|
|
STM32L47xxx, STM32L48xxx, STM32L49xxx STM32L4Axxx (Oct 2023) |
5.4.5 Power status register 1 (PWR_SR1) |
Current: This register is neither reset when exiting Standby or Shutdown mode, nor by the PWRRST bit in the RCC_APB1RSTR1 register. Expected: This register is neither reset when exiting Standby mode, nor by the PWRRST bit in the RCC_APB1RSTR1 register. |
Dec 2024 |
|
|
STM32U0
(Mar 2024) |
4.4.5 Power status register 1 (PWR_SR1) |
|||
|
STM32WBA5
(Sep 2024) |
11.4.1 External power supplies |
Current: - VDDRFPA is the external power supply for the 2.4 GHz RADIO front-end part and PA - VDDANA = 0 V to 3.6 V (must be above 1.2 V for 2.4 GHz RADIO operation), available only on STM32WBA55xx devices) Expected: - VDDRFPA is the external power supply for the 2.4 GHz RADIO front-end part and PA. VDDRFPA must be equal or lower than VDDRF. |
Dec 2024 |
|
| COMP |
STM32F303xB
(Jan 2024) |
17.5.3 COMP3 control and status register (COMP3_CSR)
17.5.4 COMP4 control and status register (COMP4_CSR)
17.5.5 COMP5 control and status register (COMP5_CSR)
17.5.6 COMP6 control and status register (COMP6_CSR)
17.5.7 COMP7 control and status register (COMP7_CSR) |
Current: Bits 3:2 COMPxMODE[1:0]: Comparator x mode (only in STM32F303xB/C and STM32F358xC devices.) Expected: Bits 3:2 COMPxMODE[1:0]: Comparator x mode (only in STM32F303xB/C and STM32F358xC devices.) 00: High speed |
Apr 2024 |
| Documen-tation conven-tions |
STM32G4
(Feb 2024) |
Table 1. STM32G4 series memory density |
Current: Missing device category: Expected:  |
Dec 2024 |
| DBG |
STM32F410
(Nov 2018) |
26.16.4 Debug MCU APB1 freeze register (DBGMCU_ |
Current: Missing "DBG_LPTIM1_STOP" bit description in "DBGMCU_APB1_FZ" register Expected: Add Bit 9 DBG_LPTIM1_STOP: LPTMI1 counter stopped when core is halted |
Oct 2024 |
|
STM32U5
(Oct 2023) |
75.8.1 BPU registers |
Current: Bit 1 KEY: Write protect key Expected: Bit 1 KEY: Write protect key |
Oct 2024 |
|
|
STM32U5
(Oct 2023) |
75.9.1 ETM registers |
Current: Bits 11:0 CCITMIN[11:0]: minimum value that can be programmed to TRCCCCTLR. Expected: Bits 11:0 CCITMIN[11:0]: minimum value that can be programmed to ETM_CCCTLR. |
Oct 2024 |
|
|
STM32U5
(Oct 2023) |
75.12.4 DBGMCU registers |
Current: For STM32U575/585 Expected: For STM32U575/585 |
Oct 2024 |
|
|
STM32F412
(Oct 2020) |
30.6.1 MCU device ID code |
Current: Bits 31:16 REV_ID(15:0): Revision identifier Expected: Bits 31:16 REV_ID(15:0): Revision identifier |
Oct 2024 |
|
|
STM32F410
(Nov 2018) |
26.6.1 MCU device ID code |
Current: Bits 31:16 REV_ID(15:0) Revision identifier Expected: Bits 31:16 REV_ID(15:0): Revision identifier |
Oct 2024 |
|
|
STM32F401xB
(Dec 2018) |
23.6.1 MCU device ID code |
Current: Bits 31:16 REV_ID[15:0] Revision identifier Expected: Bits 31:16 REV_ID(15:0): Revision identifier |
Oct 2024 |
|
| EXTI |
STM32F75xxx STM32F74xxx
(Mar 2018) |
11.9.6 Pending register (EXTI_PR) |
Current: "Reset value: undefined" Expected: "Reset value: 0x0000 0000" |
Jun 2024 |
|
STM32F72xxx STM32F73xxx
(Jun 2018) |
10.9.6 Pending register (EXTI_PR) |
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STM32G4
(Feb 2024) |
15.5.6 Pending register 1 (EXTI_PR1) 15.5.12 Pending register 2 (EXTI_PR2) |
Dec 2024 |
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| GPIO |
STM32L47xxx, STM32L48xxx, STM32L49xxx STM32L4Axxx
(Oct 2023) |
8.4 GPIO functional description |
Add section 8.3.4 I/O port state in Low-power modes |
Oct 2024 |
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STM32U5
(Oct 2023) |
13.3.12 Analog configuration
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Current: The weak pull-up and pull-down resistors are disabled by hardware. Expected: The weak pull-up is disabled by hardware. The weak pull-down is configurable. |
Oct 2024 |
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STM32U5
(Oct 2023) |
13.3.20 High-speed low-voltage mode (HSLV) |
Add sentence Caution: Setting this bit when the I/O is configured in Fm+ mode is forbidden. An I/O is in Fm+ mode when it is configured as I2C alternate function, with FMP=1 in I2C_CR1 register. PB6, PB7, PB6, PB9 can also be in Fm+ mode when PB6_FMP, PB7_FMP, PB8_FMP, PB9_FMP, respectively, is set in SYSCFG_CFGR1 register. |
Oct 2024 |
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STM32U5
(Oct 2023) |
13.4.12 GPIO high-speed low-voltage register (GPIOx_ HSLVR) (x = A to J) |
Current: Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Expected: Add:" Setting this bit when the I/O is configured in Fm+ mode is forbidden." |
Oct 2024 |
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STM32U5
(Oct 2023) |
13.3.2 I/O pin alternate function multiplexer and mapping |
Add sentence - Cortex-M33 alternate function (EVENTOUT) |
Oct 2024 |
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STM32L47xxx, STM32L48xxx, STM32L49xxx STM32L4Axxx
(Oct 2023) |
8.2 GPIO main features |
Add sentence Configurable state of each I/O in Standby mode: floating, pull-up/down, analog. |
Oct 2024 |
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STM32F410
(Nov 2018) |
6.3.2 I/O pin multiplexer and mapping |
Current: Cortex®-M4 with FPU EVENTOUT is mapped on AF15. Expected: Cortex®-M4 with FPU output EVENTOUT signal can be used by configuring the I/O pin to output on AF15. |
Oct 2024 |
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STM32F401xB
(Dec 2018) |
8.3.2 I/O pin multiplexer and mapping | |||
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STM32WBA5
(Sep 2024) |
14.4 GPIO functional description |
Expected: Add "analog pull-down" feature to GPIO mode
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Nov 2024 |
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| SAI |
STM32H523xx
(Apr 2024) |
53.4.10 PDM interface |
Expected: Remove "3. Configure the slot size (DS) to a multiple of (FRL+1)." |
Sep 2024 |
| DMA |
STM32L47xxx, STM32L48xxx, STM32L49xxx STM32L4Axxx
(Oct 2023) |
Table 43. DMA1 and DMA2 implementation |
Current: 1. HASH related DMA channel is only applicable for STM32L4Ax devices. Expected: 1. HASH related DMA channel is only applicable for STM32L4Ax/L49x devices. |
Oct 2024 |
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STM32L47xxx, STM32L48xxx, STM32L49xxx STM32L4Axxx
(Oct 2023) |
Table 45. DMA2 requests for each channel Figure 31. DMA block diagram |
Current: "3. Only available on STM32L4Ax devices." Expected: "3. Only available on STM32L4Ax/L49x devices." |
Oct 2024 |
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STM32F410
(Nov 2018) |
Table 29. DMA1 request mapping |
Expected: Remove: "DAC2 interface (on Stream 6 of Channel 7)." |
Oct 2024 |
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| DAC |
STM32F410
(Nov 2018) |
Figure 40. DAC channel block diagram 12.3 DAC output buffer enable |
Current: Several name used "DAC_OUT1", "DAC1_OUT", and "DAC1_OUT1" Expected: Use a single name "DAC_OUT" |
Oct 2024 |
| DFSDM |
STM32F412
(Oct 2020)
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14.4.3 DFSDM reset and clocks |
Expected: Remove: "Audio clock source is SAI1 clock selected by SAI1SEL[1:0] field in RCC configuration" |
Oct 2024 |
| SAES |
STM32H523xx
(Apr 2024) |
34.4.17 SAES key registers |
Current: Repeated writing of KEYSEL[2:0] with the same non-zero value only triggers the loading of DHUK or BHK if KEYVALID is set. Expected: Repeated writing of KEYSEL[2:0] with the same non-zero value only triggers the loading of DHUK or BHK if KEYVALID is cleared. |
Sep 2024 |
| DSI |
STM32U5
(Oct 2023)
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44.15.6 DSI Host LTDC polarity configuration register (DSI_LPCR) |
Current: Bit 2 HSP: HSYNC polarity Bit 1 VSP: VSYNC polarity Expected: Bit 2 HSP: HSYNC polarity |
Oct 2024 |
| HSPI |
STM32U5
(Oct 2023) |
30.7.3 HSPI device configuration register 2 (HSPI_DCR2) |
Current: Writing this bitfield automatically starts a new calibration of high-speed interface DLL Expected: Writing this bitfield automatically starts a new calibration of high-speed interface DLL |
Oct 2024 |
| FDCAN |
STM32G4
(Feb 2024) |
44.3.1 Bit timing |
Expected: Add "Note: The FDCAN requires that the CAN time quanta clock is always below or equal to the APB clock (fdcan_tq_ck < fdcan_pclk)." |
Nov 2024 |
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STM32U5
(Oct 2023) |
70 FD controller area network (FDCAN) |
Expected: Add "This section applies to STM32U53x/54x/57x/58x/59x/5Ax/5Gx devices only." |
Dec 2024 | |
| SYSCFG |
STM32U5
(Oct 2023) |
15.3.2 SYSCFG configuration register 1 (SYSCFG_ |
Current: - 0: I/O analog switches are supplied by VDDA or booster when booster is ON. - Bit 8 BOOSTEN: I/O analog switch voltage booster enable - The table below describes when bit 8 (BOOSTEN) and bit 9 (ANASWVDD) must be set or reset depending on the voltage settings. Expected: 0: If booster if OFF: I/O analog switches are supplied by VDDA if ASV=1 in PWR_SVMCR, by VDD if ASV=0. If booster is ON: I/O analog switches are supplied by booster. - Bit 8 BOOSTEN: I/O analog switch voltage booster enable. This bit has only effect when ASV=1 in PWR_SVMR, and ANASWVDD=0. -The table below describes when bit 8 (BOOSTEN) and bit 9 (ANASWVDD) must be set or reset depending on the voltage settings. When VDDA voltage is lower than 2.4 V and VDD is higher than 2.4 V, the I/O analog switch must be powered by VDD. When both VDD and VDDA voltages are lower than 2.4 V, the I/O analog switch must be powered by the output of the VDD booster. When I/O analog switches are supplied by VDDA or VDD booster, ASV must be set to 1 in PWR_SVMCR. |
Oct 2024 |
| Hash |
STM32L47xxx STM32L48xxx STM32L49xxx STM32L4Axxx
(Oct 2023) |
29 Hash processor (HASH) |
Current: This section applies to STM32L4Ax devices only. Expected: This section applies to STM32L4Ax/L49x devices only. |
Oct 2024 |
| Memory and bus architec- ture |
STM32WBA5
(Sep 2024) |
Table 4. Memory map and peripheral register boundary addresses (continued) |
Current: "AHB1" bus is from 0x0000 0000 to 0x3FFF FFFF Expected: "AHB" bus is from 0x0000 0000 to 0x3FFF FFFF |
Nov 2024 |
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STM32H745 (Jun 2023)
STM32H7A3 (Dec 2023)
STM32H742 STM32H743 (Jan 2023)
STM32H723 (Dec 2021) |
AXI interconnect - INI x AHB functionality modification register |
Current: Bit 1 WR_INC_OVERRIDE: Converts all AHB-Lite read transactions to a series of single beat AXI Expected: Bit 1 WR_INC_OVERRIDE: Converts all AHB-Lite write transactions to a series of single beat AXI transactions, and each AHB-Lite write beat is acknowledged with the AXI buffered write response. Bit 0 RD_INC_OVERRIDE: Converts all AHB-Lite read transactions to a series of single beat AXI transactions. |
Jul 2024 |
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STM32H723 (Dec 2021) |
Table 7. Register boundary addresses |
Expected: Add: |
Dec 2024 |
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STM32N647 (Apr 2024) |
Table 3. Peripheral register boundary addresses |
Current: - OTG1 to OTG1_HS Expected: - OTG1_HS |
Dec 2024 |
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| SBS |
STM32H523xx
(Apr 2024) |
14.5.4 SBS debug control register (SBS_DBGCR) |
Current: Bits 31:24 DBG_AUTH_SEC[7:0]: control debug opening secure/non-secure Expected: Bits 31:24 DBG_AUTH_SEC[7:0]: control debug opening secure/non-secure Write 0xB4 to this bitfield to open debug for secure and any other values will only open non-secure. |
Nov 2024 |
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STM32H523xx
(Apr 2024) |
14.5.9 SBS product mode and configuration register (SBS_PMCR) |
Expected: Remove: – depending on ADC12SEC secure input for ANASWVDD and IO_ANA_BOOST_EN configuration bits – depending on SDCE_SEC_EN in SBS_SECCFGR for SMPS_DIV_CLOCK_EN |
Nov 2024 |
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| System Security |
STM32H523xx
(Apr 2024) |
3.7.1 Temporal isolation using secure hide protection (HDP) |
Current: When the TrustZone security is enabled, the embedded flash memory allows to define an HDP area per watermarked-secure area of each bank (8-Kbyte page granularity). Expected: The embedded flash memory allows to define an HDP area per watermarked-secure area of each bank (8-Kbyte page granularity). |
Nov 2024 |
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STM32U5
(Oct 2023)
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System security |
Add Section: 3.6.2 RSSLIB functions The user firmware calls RSSLIB functions using RSSLIB_PFUNC C defined macro, that points to a location within non-secure system memory. Hence prior calling RSSLIB functions, the secure user firmware must define a non-secure region above this location within SAU of the Cortex®-M33. This non-secure region starts from RSSLIB_SYS_FLASH_NS_PFUNC_START up to RSSLIB_SYS_FLASH_NS_PFUNC_END. These last addresses are provided within the CMSIS device header file. The user can set this non-secure region either by using the CMSIS system partition header file or by implementing its own code for SAU setup. The CMSIS system partition header file is part of the STM32Cube firmware package. RSSLIB functions are split between non-secure callable and secure callable function. The RSS library functions are described within sections hereafter. CloseExitHDP Bootloader ID: Secure attribute: Prototype: Arguments: Description: CloseExitHDP sets the SP provided by the passed vector table, however it is up to the caller to first set the new vector table. Then it clears all general-purpose ACortex®-M33 registers (r0, r1, …) before jumping to new vector On successful execution, the function does not return and does not push LR onto the stack. |
Nov 2024 |
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| LCD |
STM32U0
(Mar 2024) |
19 Liquid crystal display controller (LCD) |
Add: Note: In the LCD chapter: |
Nov 2024 |
| I2C |
STM32G4
(Feb 2024) |
41 Inter-integrated circuit interface (I2C) |
Current: - I2C master - I2C Slave Expected: - I2C Controller - I2C Target |
Nov 2024 |
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STM32H523xx
(Apr 2024) |
48 Inter-integrated circuit interface (I2C) |
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| OCTOSPI |
STM32L552xx STM32L562xx
(Dec 2020) |
20.4.14 OCTOSPI Regular-command mode configuration |
Current: This shift is performed by an external delay block located outside the OCTOSPI. The control of this feature depends on the device implementation (see the product reference manual for more details). Expected: This shift is controlled via the RCC_DLYCFGR register. |
Dec 2024
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STM32L552xx STM32L562xx
(Dec 2020) |
20.7.2 OCTOSPI device configuration register 1 (OCTOSPI_ |
Current: Bit 3 DLYBYP: Delay block bypass Expected: Bit 3 DLYBYP: Delay block bypass |
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| Peri-pherals inter-connect matrix |
STM32H523xx
(Apr 2024) |
15.3.5 Clock sources to timers |
Current: LSE, HSI, and CSI are assigned to general purpose timer TIM2 as external inputs signals. Expected: LSE, HSI, and CSI are assigned to general purpose timer TIM2/12 as external inputs signals. |
Dec 2024 |
| Radio system |
STM32WBA5
(Sep 2024) |
9 Radio system |
Current: The 2.4 GHz RADIO is compliant with the Bluetooth 5.3, Ant+, Thread and Zigbee® specifications, and radio regulations including ETSI EN 300 328, EN 300 440, EN 301 489-17, ARIB STD-T66, FCC CFR47 part 15 section 15.205, 15.209, 15.247, and 15.249, IC RSS-139 and RSS-210. Expected: Remove "Ant+" |
Nov 2024 |
| AHB up/down converter |
STM32WL33xx (Nov 2024) |
Figure 3. AHB up/down converter |
Current: Bubble Expected: LPAWUR |
Dec 2024 |
| GTZC |
STM32WBA5 (Sep 2024) |
5.6.5 GTZC1 TZSC privilege configuration register 1 |
Current: This register can be read or written only by secure privileged transaction when corresponding GTZC1_TZSC_SECCFGR1 register bit is set to1. If a given SEC bit is not set, the equivalent PRIV bit can be read/written by non-secure privileged transaction. Expected: Remove "read" |
Dec 2024 |
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STM32U5 (Oct 2023) |
5 Global TrustZone controller (GTZC) |
Expected: Add for CFDCAN1F, FDCAN1F, FDCAN1IE, FDCAN1PRIV, FDCAN1SEC, CMPCBB6_REGF, CSRAM6F, MPCBB6_REGF and SRAM6F bits : Note: This bit is only available on some devices in the STM32U5 series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and kept at reset value. |
