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STM32 MCU reference manuals: Expected preliminary updates

KDJEM.1
ST Employee

‎2024-06-10 7:00 AM - edited ‎2025-04-07 7:53 AM

Introduction 

This article includes preliminary updates of STM32 MCU reference manuals reported since 1st January 2024. It highlights the current description requiring update and the expected one if available.

The purpose of this article is to deliver any expected updates to our MCU reference manuals prior to actual documentation releases. We wish to be transparent with our updates and provide them as fast as possible, to assist you in your design process.
This article is updated on a quarterly basis. Once these preliminary updates are manifested in the reference manuals, this article is refreshed with new information.
Moving forward, we are also working on providing reference manual releases on a more frequent basis.

IMPORTANT NOTICE - READ CAREFULLY:

  • STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to this article at any time without notice.
  • Information in this article supersedes and replaces information previously supplied in any prior versions of this article.
  • The following table gives a quick reference to the preliminary documentation updates which may be changed or improved without notice. 
  • This article will be reviewed on a quarterly basis and applied updates will be removed from the table.
  • The hyperlinks under "Doc Reference - Revision" provides a direct link to the specific document page where the description is located.

Summary of documentation updates: "STM32 MCU reference manuals"

Function Series(Lines) / Doc Reference
Revision		 Update Location  Current Description /
Expected Description 		 Date of added update
NVIC

STM32L47xxx, STM32L48xxx, STM32L49xxx  STM32L4Axxx

 

RM0351 Rev10

(Oct 2023)

Table 58. STM32L47x/
L48x/L49x/
L4Ax vector table

Current:

4. HASH available on STM32L4Ax devices only.

Expected:

4. HASH available on STM32L4Ax devices onlySTM32L4Ax/L49x devices only.

Oct 2024
RCC

 STM32H742

STM32H743

STM32H753

STM32H750

 

RM0433 Rev8

(Jan 2023)

Table 60. Kernel clock distribution overview 

Current:

Maximum allowed frequency [MHz] for ADC1,2,3 are:
VOS0 100(4)
VOS1 100(4)
VOS2 80(4)
VOS3 80(4) 

with note "4. With a duty cycle close to 50%, meaning that DIV[P/Q/R]x values shall be even. For SDMMCx, the duty cycle shall be 50% when supporting DDR."

Expected:

Maximum allowed frequency [MHz] for ADC1,2,3 are:
VOS0 80
VOS1 80
VOS2 40 
VOS3 40 

Mar 2024
 

STM32H523xx
STM32H533xx STM32H562xx
STM32H563xx  STM32H573xx

 

RM0481 Rev3
(Mar 2025)

  11.8.8 RCC PLL clock source selection register (RCC_
PLL2CFGR)		  

Current:

0: wide VCO range 192 to 836 MHz (default after reset)

Expected:

0: wide VCO range 128 to 560MHz (default after reset)

  Sep 2024

STM32H523xx
STM32H533xx STM32H562xx
STM32H563xx  STM32H573xx

 

RM0481 Rev3
(Mar 2025)

 11.8.13 RCC PLL2 fractional divider register (RCC_
PLL2FRACR)

Current:

* PLL2FRACN can be between 0 and 213- 1

Expected:

* FRACN2 can be between 0 and (2^13)-1

 Sep 2024

STM32H723
STM32H733, STM32H725
STM32H735 STM32H730

RM0468 Rev3

(Dec 2021)

 8.7.39 RCC AHB3 clock register (RCC_
AHB3ENR)

Expected:

KDJEM1_2-1735823513460.png		 Dec 2024

STM32H723
STM32H733, STM32H725
STM32H735 STM32H730

RM0468 Rev3

(Dec 2021)

 8.7.28 RCC AHB1 peripheral reset register(RCC_
AHB1RSTR)

Current:

Bit 1 DMA2RST: DMA2 block reset
Set and reset by software.
0: does not reset DMA2 block (default after reset)
1: resets DMA2 block
Bit 0 DMA1RST: DMA1 block reset
Set and reset by software.
0: does not reset DMA1 block (default after reset)
1: resets DMA1 block

Expected:

Bit 1 DMA2RST: DMA2 and DMAMUX1 reset
Set and cleared by software.
0: No effect
1: Reset DMA2 and DMAMUX1
Bit 0 DMA1RST: DMA1 and DMAMUX1 reset
Set and cleared by software.
0: No effect
1: Reset DMA1 and DMAMUX1

 Dec 2024

STM32H723
STM32H733, STM32H725
STM32H735 STM32H730

RM0468 Rev3

(Dec 2021)

 8.7.30 RCC AHB4 peripheral reset register (RCC_
AHB4RSTR)

Current:

Bit 21 BDMARST: BDMA block reset
Set and reset by software.
0: does not reset the BDMA block (default after reset)
1: resets the BDMA block

Expected:

Bit 21 BDMARST: BDMA block reset
Set and reset by software.
0: does not reset the BDMA block (default after reset)
1: resets the BDMA and DMAMUX2

 Dec 2024

STM32U0

 

RM0503 Rev2

(Mar 2024)

 5.2.6 LSE clock

Expected:

Add:

Distribution of the LSE clock out of RTC block is gated by default to achieve lowest power consumption. Set LSESYSEN bit in the RCC-BDCR to release clock distribution to LCD, SYSCLK, LSCO and MCO.

 Dec 2024

STM32U0

 

RM0503 Rev2

(Mar 2024)

 5.4.22 RTC domain control register (RCC_BDCR)

Current:

Bit 2 LSEBYP: LSE oscillator bypass
Set and cleared by software to bypass the LSE oscillator (in debug mode).

Expected:

Bit 2 LSEBYP: LSE oscillator bypass
Set and cleared by software to bypass the LSE oscillator.

 Dec 2024

STM32F205xx, STM32F207xx STM32F215xx  STM32F217xx

 

RM0033 Rev9

(Feb 2021)

 5.3.20 RCC Backup domain control register (RCC_BDCR)

Current:

Bit 2 LSEBYP: External low-speed oscillator bypass
Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the LSE clock is disabled.

Expected:

Bit 2 LSEBYP: External low-speed oscillator bypass
Set and cleared by software to bypass oscillator. This bit can be written only
when the LSE clock is disabled.

 Mar 2025

STM32F303xB
STM32F303xC
STM32F303xD
STM32F303xE
STM32F303x6
STM32F303x8
STM32F328x8
STM32F358xC STM32F398xE

 

RM0316 Rev10

(Jan 2024)  

 Figure 14. STM32F303xDxE and STM32F398xE clock tree

Current:

KDJEM1_0-1743682582440.png

Expected:

KDJEM1_1-1743682628156.png		 Mar 2025

STM32WBA6

RM0515 Rev2

(Feb 2025)


 

 12.8.9 RCC clock interrupt enable register (RCC_CIER)

Expected:

- Add note to LSI2RDYIE:

Note: If the LSI2 is ready (LSI2RDY in RCC_BDCR1 is 1) before enabling LSI2RDYIE, the LSI2RDYF in RCC_CIFR will not be set and no interrupt is generated.

- Add note to PLL1RDYIE:

Note: If the PLL1 is ready (PLL1RDY in RCC_CR is 1) before enabling PLL1RDYIE, the PLL1RDYF in RCC_CIFR will not be set and no interrupt is generated.

- Add note to HSERDYIE:

Note: If the HSE is ready (HSERDY in RCC_CR is 1) before enabling HSERDYIE, the HSERDYF in RCC_CIFR will not be set and no interrupt is generated.

- Add note to HSIRDYIE:

Note: If the HSI16 is ready (HSIRDY in RCC_CR is 1) before enabling HSIRDYIE, the HSIRDYF in RCC_CIFR will not be set and no interrupt is generated.

- Add note to LSERDYIE:

Note: If the LSE is ready (LSERDY in RCC_BDCR1 is 1) before enabling LSERDYIE, the LSERDYF in RCC_CIFR will not be set and no interrupt is generated.

- Add note to LSI1RDYIE:

Note: If the LSI1 is ready (LSI1RDY in RCC_BDCR1 is 1) before enabling LSI1RDYIE, the LSI1RDYF in RCC_CIFR will not be set and no interrupt is generated.

 Mar 2025
FLASH

STM32H745
STM32H755 STM32H747
STM32H757

RM0399 Rev4

(Jun 2023)

 

 

STM32H7A3
STM32H7B3 STM32H7B0

RM0455 Rev11

(Dec 2023)

 

 

STM32H742 STM32H743
STM32H753 STM32H750

RM0433 Rev8

(Jan 2023)

 

 

STM32H723
STM32H733 STM32H725
STM32H735 STM32H730

RM0468 Rev3

(Dec 2021)

 

 

STM32H7Rx/
7Sx

RM0477 Rev8
(Dec 2024)

FLASH erase operations

Current:

"1. Check and clear (optional) all the error flags due to previous programming/erase operation. Refer to Section 5.7: FLASH error management for details."

Expected:

"Remove (optional) word."

 

Aug 2024
Table xx. Flash interrupt request

Expected:

Add notes to Clear flag to resume operation for:

-Write protection error: Check this flag after an erase operation.

-Programming sequence error and Inconsistency error: Check and clear all the (PGSEER, INCERR, STRBERR) error flags due to previous write operation. 

 Aug 2024

STM32L4+

 

RM0432 Rev9

(Jun 2021)

 Table 9. Flash module - 1 Mbyte single-bank organization, DB1M = 0
(128 bits read width)

Expected:

KDJEM1_3-1727864262617.png

Sep 2024

STM32L4+

 

RM0432 Rev9

(Jun 2021)

 3.7.8 Flash option register (FLASH_OPTR)

Current:

"Note: For 1-Mbyte and 512-Kbyte Flash memory devices, do not care about DBANK"

Expected:

"Note: For 1-Mbyte and 512-Kbyte Flash memory devices, the DBANK option bit must not be used and must be kept at its ST production value of “1”."

Sep 2024

STM32L0x1

RM0377 Rev10

(Feb 2022)

 3.7.8 Option bytes register (FLASH_OPTR)

Current:

All bits on FLASH_OPTR register are set to read only.

Expected:

RDPROT -> read-only
WPRMOD -> read-only
BOR_LEV[3:0] -> read-write
WDG_SW -> read-write
nRTS_STOP -> read-write
nRST_STDBY -> read-write
BOOT1 -> read-only

Mar 2025
TIM

STM32F469xx  STM32F479xx

RM0386 Rev6

(May 2024) 

22.4.9 TIM1&TIM8 capture/
compare enable register (TIMx_CCER)

Current:

Bits 15:14 Reserved, must be kept at reset value.

Expected:

Bit 15 CC4NP: Capture/Compare 4 complementary output polarity refer to CC1NP description 
Bit 14 Reserved, must be kept at reset value.

Dec 2024

STM32F413
STM32F423

RM0430 Rev9

(Oct 2024)

17.4.9 TIM1&TIM8 capture/
compare enable register (TIMx_CCER)

STM32H723
STM32H733 STM32H725
STM32H735 STM32H730

RM0468 Rev3

(Dec 2021)

44.3.11 Combined PWM mode

Current:

When a given channel is used as combined PWM channel, its secondary channel must be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the other in Combined PWM mode 2)

Expected:

When a given channel is used as combined PWM channel, its secondary channel must be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the other in PWM mode 2)

Dec 2024
LPUART

STM32L0x3

 

RM0367 Rev8

(Feb 2022)

Table 150. Error calculation for programmed baud rates at fck = 32 MHz

Current:

Table 150. Error calculation for programmed baud rates at fck = 32 MHz

Expected:

Table 150. Error calculation for programmed baud rates at fck = 32.768 KHz

May 2024
RTC

STM32H523xx
STM32H533xx STM32H562xx
STM32H563xx  STM32H573xx

 

RM0481 Rev3

(Apr 2024)

Table 495. PI8 configuration

Current:

"Table 495. PI8 configuration"

Expected:

"Table 495. PI8/PB2 configuration"

Jun 2024

STM32H503 

RM0492 Rev3

(Nov 2024)

Table 243. RTC register map and reset values (continued)

Expected:

 RTC_OR register have to be removed

 

Mar 2025
ETH

STM32H723
STM32H733
STM32H725
STM32H735
STM32H730

 

RM0468 Rev3

(Dec 2021)

Table 543. Ethernet peripheral pins

 

Expected:

Remove "ETH_PHY_INTN" from Table Ethernet peripheral pins

Apr 2024

STM32H742 STM32H743
STM32H753 STM32H750

 

RM0433 Rev8

(Jan 2023)

Table 522. Ethernet peripheral pins

Current:

 "ETH_PHY_INTN"

Expected:

Remove "ETH_PHY_INTN" from Table Ethernet peripheral pins

May 2024

STM32H523xx
STM32H533xx STM32H562xx
STM32H563xx  STM32H573xx

 

RM0481 Rev3

(Mar 2025)

 

57 Ethernet (ETH): media access control
(MAC) with DMA controller

Expected:

KDJEM1_1-1727863347619.png

Sep 2024

STM32F205xx, STM32F207xx STM32F215xx  STM32F217xx

 

RM0033 Rev9

(Feb 2021)

Figure 328. Frame transmission in MMI and RMII modes

Expected:

KDJEM1_0-1743677382407.png

Mar 2025
PWR

 STM32U0

 

RM0503 Rev2

(Mar 2024)

4.4.2 Power control register 2 (PWR_CR2)

Current:

Bit 10 USV(1)

Bit 4 PVME1(1)

with note "1. Available on STM32U0 devices only."

Expected:

Bit 10 USV(1)

Bit 4 PVME1(1)

with note "1. Available on STM32U0x3xx devices only."

Apr 2024

STM32U0

 

RM0503 Rev2

(Mar 2024)

4.4.2 Power control register 2 (PWR_CR2)

Current:

"1. Available on STM32U0x3xx devices only." 

Expected:

Remove note "1. Available on STM32U0x3xx devices only."

Jul 2024

STM32F76xxx  STM32F77xxx

 

RM0410 Rev5

(Jul 2024)

4.3 Low-power modes

Current:

"The MCU exits from Standby low-power mode through an external reset (NRST pin), an IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event occurs" 

Expected:

"The MCU exits from Standby low-power mode through an external reset (NRST pin), an IWDG reset, a rising or falling on one of the enabled WKUPx pins or a RTC event occurs"

Aug 2024

STM32L47xxx STM32L48xxx STM32L49xxx  STM32L4Axxx

 

RM0351 Rev10

(Oct 2023)

Table 23. Functionalities depending on the working mode

Current:

5. Not available on STM32L47x/L48x/L49x devices.

Expected:

5. Not available on STM32L47x/L48x devices.”

Oct 2024

STM32L47xxx STM32L48xxx STM32L49xxx  STM32L4Axxx

 

RM0351 Rev10

(Oct 2023)

6.4.11 AHB2 peripheral reset register (RCC_
AHB2RSTR)

Current:

Bit 17 HASHRST: Hash reset (this bit is reserved for STM32L47x/L48x/L49x devices)

Expected:

Bit 17 HASHRST: Hash reset(this bit is reserved for STM32L47x/L48x devices)

Oct 2024

STM32L47xxx STM32L48xxx STM32L49xxx  STM32L4Axxx

 

RM0351 Rev10

(Oct 2023)

6.4.17 AHB2 peripheral clock enable register (RCC_
AHB2ENR)

Current:

Bit 17 HASHEN: HASH clock enable (this bit is reserved for STM32L47x/L48x/L49x devices)

Expected:

Bit 17 HASHEN: HASH clock enable (this bit is reserved for STM32L47x/L48x devices)

Oct 2024

STM32L47xxx, STM32L48xxx, STM32L49xxx  STM32L4Axxx

 

RM0351 Rev10

(Oct 2023)

6.4.23 AHB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_
AHB2SMENR)

Current:

Bit 17 HASHSMEN: HASH clock enable during Sleep and Stop modes (this bit is reserved for STM32L47x/L48x/L49x devices)

Expected:

Bit 17 HASHEN: HASH clock enable (this bit is reserved for STM32L47x/L48x devices)

 Oct 2024

STM32L47xxx, STM32L48xxx, STM32L49xxx  STM32L4Axxx

RM0351 Rev10

(Oct 2023)

5.3.10 Shutdown mode

Current:

Exiting Shutdown mode

Expected:

Add

WUFx bits in the PWR_SR1 register are cleared by power-on reset during Shutdown mode exit. They will be seen as set only if the related wake-up signal is longer than release of the power-on reset signal.

Dec 2024


 

 STM32U0

 

RM0503 Rev2

(Mar 2024)

4.3.10 Shutdown mode

STM32U0

 

RM0503 Rev2

(Mar 2024)

Table 30. Shutdown mode

Current:

WKUPx pin edge, RTC event, external Reset in NRST pin

Expected:

WKUPx pin edge, RTC event, TAMP event, external Reset on NRST pin

Dec 2024

STM32L47xxx, STM32L48xxx, STM32L49xxx  STM32L4Axxx

RM0351 Rev10

(Oct 2023)

5.4.5 Power status register 1 (PWR_SR1)

Current:

This register is neither reset when exiting Standby or Shutdown mode, nor by the PWRRST bit in the RCC_APB1RSTR1 register.

Expected:

This register is neither reset when exiting Standby mode, nor by the PWRRST bit in the RCC_APB1RSTR1 register.

Dec 2024

 STM32U0

 

RM0503 Rev2

(Mar 2024)

4.4.5 Power status register 1 (PWR_SR1)

STM32L41xxx
STM32L42xxx
STM32L43xxx
STM32L44xxx
STM32L45xxx
STM32L46xxx

RM0394 Rev5
(Dec 2024)

5.4.3 Power control register 3 (PWR_CR3)
5.4.4 Power control register 4 (PWR_CR4)
5.4.9 Power Port A pull-down control register (PWR_PDCRA)
5.4.10 Power Port B pull-up control register (PWR_PUCRB)
5.4.11 Power Port B pull-down control register (PWR_PDCRB)
5.4.12 Power Port C pull-up control register (PWR_PUCRC)
5.4.13 Power Port C pull-down control register (PWR_PDCRC)
5.4.14 Power Port D pull-up control register (PWR_PUCRD)
5.4.15 Power Port D pull-down control register (PWR_PDCRD)

Mar 2025

STM32L41xxx
STM32L42xxx
STM32L43xxx
STM32L44xxx
STM32L45xxx
STM32L46xxx

RM0394 Rev5
(Dec 2024)

5.3.9 Standby mode

Current:

The SBF status
flag in the Power control register 3 (PWR_CR3)

Expected:

The SBF status flag in the Power status register (PWR_SR1)

Mar 2025

STM32WBA6

RM0515 Rev2

(Feb 2025)

 

Table 88. Functionalities depending on the working mode

Expected:

Remove HSI48

Mar 2025
COMP

STM32F303xB
STM32F303xC
STM32F303xD
STM32F303xE
STM32F303x6
STM32F303x8
STM32F328x8
STM32F358xC STM32F398xE

 

RM0316 Rev10

(Jan 2024) 

17.5.3 COMP3 control and status register (COMP3_CSR)

 

17.5.4 COMP4 control and status register (COMP4_CSR)

 

17.5.5 COMP5 control and status register (COMP5_CSR)

 

17.5.6 COMP6 control and status register (COMP6_CSR)

 

17.5.7 COMP7 control and status register (COMP7_CSR)

Current:

Bits 3:2 COMPxMODE[1:0]: Comparator x mode (only in STM32F303xB/C and STM32F358xC devices.)
These bits control the operating mode of the comparator x and allows to adjust the speed/consumption.
00: Ultra-low power
01: Low-power
10: Medium speed
11: High speed

Expected:

Bits 3:2 COMPxMODE[1:0]: Comparator x mode (only in STM32F303xB/C and STM32F358xC devices.)
These bits control the operating mode of the comparator x and allows to adjust the speed/consumption.

00: High speed 
01: Medium speed
10: Low-power
11: Ultra-low-power

Apr 2024
DBG 

STM32U5

 

RM0456 Rev6

(Jan 2025)

75.8.1 BPU registers

Current:

Bit 1 KEY: Write protect key
A write to FPB_CTRLR register is ignored if this bit is not set to 1.
Bit 0 ENABLE: FPB enable

Expected:

Bit 1 KEY: Write protect key
A write to BPU_CTRLR register is ignored if this bit is not set to 1.
Bit 0 ENABLE: BPU enable

Oct 2024

STM32WBA6

RM0515 Rev2

(Feb 2025)

45.13.7 DBGMCU registers

Current:

DBGMCU identity code register (DBGMCU_IDCODER)

Expected:

DBGMCU identity code register (DBGMCU_IDCODE)

Mar 2025
GPIO

STM32L47xxx, STM32L48xxx, STM32L49xxx  STM32L4Axxx

 

RM0351 Rev10

(Oct 2023)

8.4 GPIO functional description 

Add section

8.3.4 I/O port state in Low-power modes
In Standby and Shutdown modes, the GPIO peripheral is not active, and its configuration is forced externally by the PWR control. The PWR_PUCRx and PWR_PDCRx registers
should be used to fix the GPIO pin states during deep low-power modes to prevent disturbing external components and buses, and to optimize power consumption.

Oct 2024

STM32L47xxx, STM32L48xxx, STM32L49xxx  STM32L4Axxx

 

RM0351 Rev10

(Oct 2023)

 8.2 GPIO main features

Add sentence

Configurable state of each I/O in Standby mode: floating, pull-up/down, analog.

Oct 2024

STM32F205xx, STM32F207xx STM32F215xx  STM32F217xx

 

RM0033 Rev9

(Feb 2021)

 6.3.2 I/O pin multiplexer and mapping

Current:

• Cortex®-M3 EVENTOUT is mapped on AF15
This structure is shown in Figure 14 below.

Expected:

• Cortex®-M3 output EVENTOUT signal can be used by configuring the I/O pin to output on AF15.
An event can be signaled through the configured pin after executing SEV assembly instruction. It can be used as internal trigger for some peripheral or externally on related GPIO.
This structure is shown in Figure 14. Selecting an alternate function below.

Mar 2025

STM32H723
STM32H733 STM32H725
STM32H735 STM32H730

RM0468 Rev3
(Dec 2021)

 11.3.11 I/O compensation cell

Add:

Note: The activation of the I/O Compensation Cell is recommended with communication interfaces (GPIO, SPI, FMC, OSPI ...) when operating at high frequencies (please refer to product datasheet)
The I/O Compensation Cell activation procedure requires:
- The activation of the CSI clock
- The activation of the SYSCFG clock
- Enabling the I/O Compensation Cell: setting bit [0] of register SYSCFG_CCCSR

Mar 2025

STM32WBA6

RM0515 Rev2

(Feb 2025)

 14.4.14 High-speed low-voltage mode (HSLV)

Current:

Caution: The I/O HSLV configuration bit cannot must not be set if the I/O supply (VDD or VDDIO2) is above 2.7 V.

Expected:

Caution: The I/O HSLV configuration bit must not be set if the I/O supply (VDD or VDDIO2) is above 2.7 V.

Mar 2025
DMA

STM32L47xxx, STM32L48xxx, STM32L49xxx  STM32L4Axxx

 

RM0351 Rev10

(Oct 2023)

Table 43. DMA1 and DMA2 implementation
(1)

Current:

1. HASH related DMA channel is only applicable for STM32L4Ax devices. 

Expected:

1. HASH related DMA channel is only applicable for STM32L4Ax/L49x devices.

Oct 2024

STM32L47xxx, STM32L48xxx, STM32L49xxx  STM32L4Axxx

 

RM0351 Rev10

(Oct 2023)

Table 45. DMA2 requests for each channel

Figure 31. DMA block diagram

Current:

"3. Only available on STM32L4Ax devices."

Expected:

"3. Only available on STM32L4Ax/L49x devices."

Oct 2024
Hash

STM32L47xxx STM32L48xxx STM32L49xxx  STM32L4Axxx

 

RM0351 Rev10

(Oct 2023)

29 Hash processor (HASH)

Current:

This section applies to STM32L4Ax devices only.

Expected:

This section applies to STM32L4Ax/L49x devices only.

Oct 2024
Memory
and 
bus
architec-
ture

STM32H745
STM32H755 STM32H747
STM32H757

RM0399 Rev4

(Jun 2023)

 

 

STM32H7A3
STM32H7B3 STM32H7B0

RM0455 Rev11

(Dec 2023)

 

 

STM32H742 STM32H743
STM32H753 STM32H750

RM0433 Rev8

(Jan 2023)

 

 

STM32H723
STM32H733 STM32H725
STM32H735 STM32H730

RM0468 Rev3

(Dec 2021)

AXI interconnect - INI x AHB functionality modification register
(AXI_INIx_FN_
MOD_AHB)

Current:

Bit 1 WR_INC_OVERRIDE: Converts all AHB-Lite read transactions to a series of single beat AXI
transactions.

Bit 0 RD_INC_OVERRIDE: Converts all AHB-Lite write transactions to a series of single beat AXI
transactions, and each AHB-Lite write beat is acknowledged with the AXI buffered write
response.

 Expected:

Bit 1 WR_INC_OVERRIDE: Converts all AHB-Lite write transactions to a series of single beat AXI transactions, and each AHB-Lite write beat is acknowledged with the AXI buffered write response.

Bit 0 RD_INC_OVERRIDE: Converts all AHB-Lite read transactions to a series of single beat AXI transactions.

Jul 2024

STM32H723
STM32H733, STM32H725
STM32H735 STM32H730

RM0468 Rev3

(Dec 2021)

Table 7. Register boundary addresses

Expected:

Add:
 Boundary address: 0x5802 7000 0x5802 7FFF, Peripheral: RAMECC_D3 

Dec 2024

STM32F303xB
STM32F303xC
STM32F303xD
STM32F303xE
STM32F303x6
STM32F303x8
STM32F328x8
STM32F358xC STM32F398xE

 

RM0316 Rev10

(Jan 2024) 

Figure 1. STM32F303xB/C and STM32F358xC system architecture

Figure 2. STM32F303x6/8 and STM32F328x8 system architecture 

Figure 3. STM32F303xDxE and STM32F398xE system architecture

Current:

FLTIF

Expected:

FLITF

 

Mar 2025
LCD

 STM32U0

 

RM0503 Rev2

(Mar 2024)

19 Liquid crystal display controller (LCD)

Add:

Note: In the LCD chapter:
To operate LCD with the LSE clock, the clock source must be released for system use. Set LSESYSEN in the RCC-BDCR.

Nov 2024
OCTOSPI

STM32L552xx  STM32L562xx

 

RM0438 Rev7

(Dec 2020)

20.4.14 OCTOSPI Regular-command mode configuration

Current:

This shift is performed by an external delay block located outside the OCTOSPI. The control of this feature depends on the device implementation (see the product reference manual for more details).

Expected:

This shift is controlled via the RCC_DLYCFGR register. 

Dec 2024


 

STM32L552xx  STM32L562xx

 

RM0438 Rev7

(Dec 2020)

20.7.2 OCTOSPI device configuration register 1 (OCTOSPI_
DCR1)

Current:

Bit 3 DLYBYP: Delay block bypass
0: The internal sampling clock (called feedback clock) or the DQS data strobe external signal is delayed by the delay block (for more details on this block, refer to the dedicated section of the reference manual as it is not part of the OCTOSPI peripheral)

Expected:

Bit 3 DLYBYP: Delay block bypass
0: The internal sampling clock (called feedback clock) or the DQS data strobe external signal is delayed by the delay block (for more details on this block, refer to the OCTOSPI delay configuration register (RCC_DLYCFGR))
Device electronic signature

STM32H723
STM32H733 STM32H725
STM32H735 STM32H730

RM0468 Rev3

(Dec 2021)

66.4 Package data register

Add:

KDJEM1_0-1743690519491.png

 

Mar 2025
OTP

STM32N647
STM32N657

RM0486 Rev2
(Jan 2025)

Table 18. OTP fuse description (lower OTP region)

Expected:

 iomgr_port: reserved

iomgr_muxen: reserved

 

Mar 2025
SYSCFG

STM32C0

RM0490 Rev5

(Dec 2024)

9.1.3 SYSCFG configuration register 3 (SYSCFG_
CFGR3)

Current:

Bits 3:2 PINMUX1[1:0]: Pin GPIO multiplexer 1
This bitfield is set and cleared by software. It selects an active GPIO on a pin.
Condition: STM32C011x - GPIO assigned to SO8 pin 4

Expected:

Bits 3:2 PINMUX1[1:0]: Pin GPIO multiplexer 1
This bitfield is set and cleared by software. It selects an active GPIO on a pin.
Condition: STM32C011x - GPIO assigned to SO8 pin 4 or WLCSP12 ball F3

Mar 2025
TAMP

STM32H503 

RM0492 Rev3

(Nov 2024)

33.6.16 TAMP option register (TAMP_OR)

Add section:

33.6.16 TAMP option register (TAMP_OR)
This register can be protected against non-privileged access. Refer to Section47.3.7: TAMP privilege protection modes.
Address offset: 0x50
Backup domain reset value: 0x0000 0000
System reset: not affected
Bits 31:10Reserved, must be kept at reset value.
Bit 9 IN3_RMP: TAMP_IN3 mapping
0: TAMP_IN3 is on PC1
1: TAMP_IN3 is on PE6
Bits 8:3 Reserved, must be kept at reset value.
Bits 2:1 OUT3_RMP[1:0]: TAMP_OUT3 mapping
00: TAMP_OUT3 is on PC13
01: Reserved
10: TAMP_OUT3 is on PE3
11: TAMP_OUT3 is on PA2
Bit 0 Reserved, must be kept at reset value.

Mar 2025
System security

STM32H523xx

STM32H533xx STM32H562xx
STM32H563xx  STM32H573xx

RM0481 Rev3

(Mar 2025)

Table 20. Main product life cycle transitions

Current:

The product is returned for analysis to field return centers. Analysis is possible by opening it
partially, or by launching a partial or a full regression. Such accesses require provisioning, including certificates provided by the vendor. 

Expected:

Add: STMicroelectronics does not perform analysis on defective parts in closed or locked states.

Mar 2025

STM32H503

RM0492 Rev3

(Nov 2024)

Table 5. Main product life-cycle transitions

 

Version history
Last update:
‎2025-04-07 7:53 AM
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